Phase-locked loop

"PLL" redirects here. For the chemical substance polylysine, see polylysine;

for the Rubik's Cube Permutation of Last Layer, see Fridrich Method;

for the spinal ligament, see Posterior longitudinal ligament.

A phase-locked loop or phase lock loop (PLL) is a control system that tries to generate an output signal whose phase is related to the phase of the input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector that compares the phase of the signal derived from the oscillator to an input signal. The signal from the phase detector is used to control the oscillator in a feedback loop. The circuit compares the phase of the input signal with the phase of a signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched.

Frequency is the derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.

Phase-locked loops are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.

Contents

Practical analogies

Automobile race analogy

For a practical idea of what is going on, consider an auto race. There are many cars, and each of them wants to go around the track as fast as possible. Each lap corresponds to a complete cycle, and each car will complete dozens of laps per hour. The number of laps per hour (a speed) is a frequency, but the number of laps (a distance) corresponds to a phase. At one instant, car 3 may have gone 37.23 laps.

During most of the race, each car is on its own and is trying to beat every other car on the course. However, if there is an accident, a pace car comes out to set a safe speed. None of the race cars are permitted to pass the pace car (or the race cars in front of them), but each of the race cars want to stay as close to the pace car as it can. While it is on the track, the pace car is a reference, and the race cars become phase-locked loops. Each driver will measure the phase difference (a distance in laps) between him and the pace car. If the driver is far away, he will increase his engine speed (the VCO) to close the gap. If he's too close to the pace car, he will slow down. The result is all the race cars lock on to the phase of the pace car. The cars travel around the track in a tight group that is a small fraction of a lap.

Clock analogy

Phase can be proportional to time[1], so a phase difference can be a time difference. Clocks are, with varying degrees of accuracy, phase-locked (time-locked) to a master clock.

Left on its own, each clock will mark time at slightly different rates. A wall clock, for example, might be fast by a few seconds per hour compared to the reference clock at NIST. Over time, that time difference would become substantial.

To keep his clock in synch, each week the owner compares the time on his wall clock to a more accurate clock (a phase comparison), and he resets his clock. Left alone, the wall clock will continue to diverge from the reference clock at the same few seconds per hour rate.

Some clocks have a timing adjustment (a fast-slow control). When the owner compared his wall clock's time to the reference time, he noticed that his clock was too fast. Consequently, he could turn the timing adjust a small amount to make the clock run a little slower. If things work out right, his clock will be more accurate. Over a series of weekly adjustments, the wall clock's notion of a second would agree with the reference time (within the wall clock's stability).

History

Automatic synchronization of electronic oscillators was described in 1923.[2] Earliest research towards what became known as the phase-locked loop goes back to 1932, when British researchers developed an alternative to Edwin Armstrong's superheterodyne receiver, the Homodyne or direct-conversion receiver. In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original modulation information. The intent was to develop an alternative receiver circuit that required fewer tuned circuits than the superheterodyne receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction signal was applied to the oscillator, maintaining it in the same phase and frequency as the desired signal. The technique was described in 1932, in a paper by Henri de Bellescize, in the French journal L'Onde Électrique.[3][4][5]

In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronization pulses in the broadcast signal.[6]

When Signetics introduced a line of monolithic integrated circuits that were complete phase-locked loop systems on a chip in 1969,[7] applications for the technique multiplied. A few years later RCA introduced the "CD4046" CMOS Micropower Phase-Locked Loop, which became a popular integrated circuit.

Structure and function

Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure.

Block diagram of a PLL (without filter)

Both analog and digital PLL circuits include four basic elements:

Variations

There are several variations of PLLs. Some terms that are used are analog phase-locked loop (APLL or LPLL), digital phase-locked loop (DPLL), all digital phase-locked loop (ADPLL), and software phase-locked loop (SPLL).

An analog PLL uses components that have analog (linear) outputs.

The term DPLL has some confusion, but it implies that at least some of the phase-locked loop components are digital. There may be digital phase detector or a digital divider, for example, but the VCO may be analog. For some, a DPLL is an ADPLL.

The term ADPLL uses all digital components. In place of a voltage-controlled oscillator (VCO), a DPLL may use a local reference clock and a variable dividing counter under digital control to create the equivalent oscillator function.[8]

The SPLL is an ADPLL implemented in software. The implementation may be done on a digital signal processor or on a general purpose computer.

DPLLs are easier to design and implement, and are less sensitive to voltage noise than analog PLLs, however they typically suffer from higher phase noise due to the quantization error of using a non-analog oscillator. For this reason digital phase locked loops are not well-suited to synthesizing higher frequencies or handling high frequency reference signals. DPLLs are sometimes used for data recovery.

Modeling

Phase domain view linearizes system. Standard control system.

Analog straightforward. Digital can have s or z domain view.

There are non-linear behaviors.

Performance parameters

Type and order.

Applications

Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.

Clock recovery

Some data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator. Typically, some sort of redundant encoding is used; 8B10B is very common.

Deskewing

If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a Delay-Locked Loop (DLL) is frequently used.[9]

Clock generation

Many electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.

Spread spectrum

All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies (such as the FCC in the United States) put limits on the emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen on broadcast FM radio channels, which have a bandwidth of several tens of kilohertz.

Clock distribution

PLL,usage.png

Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched. From a control theory perspective, the PLL is a special case of the Kalman filter.

PLLs are ubiquitous—they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference.

Jitter and noise reduction

One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset (also called the steady-state phase error). The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.

Phase noise is another type of jitter observed in PLLs, and is mostly caused by the amplifier elements used in the circuit. Some technologies are known to perform better than others in this regard. The best digital PLLs are constructed with emitter-coupled logic (ECL) elements, at the expense of high power consumption. To keep phase noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor logic (TTL) or CMOS.

Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called supply and substrate noise rejection. The higher the noise rejection, the better.

To further improve the phase noise of the output oscillation, an injection locked oscillator can be employed following the voltage controlled oscillator in the PLL.

Frequency Synthesis

In digital wireless communication systems (GSM, CDMA etc.), PLL's are used to provide the local oscillator (LO) for up-conversion during transmission and down-conversion during reception. In most cellular handsets this function has been largely integrated into a single integrated circuit to reduce the cost and size of the handset. However, due to the high performance required of base station terminals, the transmission and reception circuits are built with discrete components to achieve the levels of performance required. GSM LO modules are typically built with a frequency synthesizer integrated circuit and discrete resonator VCO's.

Frequency synthesizer manufacturers include Analog Devices[10], National Semiconductor and Texas Instruments. VCO manufacturers include Sirenza, Z-Communications, Inc. (Z-COMM)

Other applications include:

Analog phase-locked loop

Basic design

Phase-locked loop block diagram

A phase detector compares two input signals and produces an error signal which is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the VCO frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.

Analog phase locked loops are generally built with a phase detector, low pass filter and voltage-controlled oscillator (VCO) placed in a negative feedback closed-loop configuration. There may be a frequency divider in the feedback path or in the reference path, or both, in order to make the PLL's output signal frequency an integer multiple of the reference. A non integer multiple of the reference frequency can be created by replacing the simple divide-by-N counter in the feedback path with a programmable pulse swallowing counter. This technique is usually referred to as a fractional-N synthesizer or fractional-N PLL.

The oscillator generates a periodic output signal. Assume that initially the oscillator is at nearly the same frequency as the reference signal. Then, if the phase from the oscillator falls behind that of the reference, the phase detector changes the control voltage of the oscillator, so that it speeds up. Likewise, if the phase creeps ahead of the reference, the phase detector changes the control voltage to slow down the oscillator. Since initially the oscillator may be far from the reference frequency, practical phase detectors may also respond to frequency differences, so as to increase the lock-in range of allowable inputs.

The block commonly called a low pass filter generally has two distinct functions.

The primary function is to determine loop dynamics, also called "stability". This is how the loop responds to disturbances, such as changes in the reference frequency, changes of the feedback divider, or at startup. Common considerations are the range over which the loop can achieve lock (pull-in range or lock range), how fast the loop achieves lock (lock time or lock-up time) and overshoot (damping). Depending on the application, this may require one

The second common consideration is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output that is then applied to the VCO control input. This frequency modulates the VCO and produces FM sidebands commonly called "reference spurious". The low pass characteristic of this block can be used to attenuate this energy, but at times a band reject "notch" may also be needed.

The design of this block can be dominated by either of these considerations, or can be a complex process juggling the interactions of the two.

Depending on the application, either the output of the controlled oscillator, or the control signal to the oscillator, provides the useful output of the PLL system.

It should also be noted that the feedback is not limited to a frequency divider. This element can be other elements such as a frequency multiplier, or a mixer. The multiplier will make the VCO output a sub-multiple (rather than a multiple) of the reference frequency. A mixer can translate the VFO frequency by a fixed offset. It may also be a combination of these. An example being a divider following a mixer; this allows the divider to operate at a much lower frequency than the VCO without a loss in loop gain.

Elements

Phase detector

The two inputs of the phase detector (PD) are the reference input (Fi) and the feedback from the voltage controlled oscillator (VCO). The PD output controls the VCO such that the phase difference between the two inputs is held constant, making it a negative feedback system.

There are several types of phase detectors in the two main categories of analog and digital.

Analog phase detector

The phase detector needs to compute the phase difference of its two input signals. Let α be the phase of the reference input and β be the phase derived from the VCO. The actual input signals to the phase detector, however, are not α and β, but rather sinusoids such as sin(α) and cos(β). In general, computing the phase difference would involve computing the arcsine and arccosine of each normalized input (to get an ever increasing phase) and doing a subtraction. Such an analog calculation is difficult. Fortunately, the calculation can be simplified by using some approximations.

Assume that the phase differences will be small (much less than 1 radian, for example). The small-angle approximation for the sine function and the sine angle addition formula yield:

\alpha - \beta \approx \sin(\alpha-\beta) = \sin \alpha \cos\beta - \sin \beta \cos \alpha

The expression suggests a quadrature phase detector can be made by summing the outputs of two multipliers. The quadrature signals may be formed with phase shift networks. Two common implementations for multipliers are the double balanced diode mixer (diode ring) and the four-quadrant multiplier (Gilbert cell).

Instead of using two multipliers, a more common phase detector uses a single multiplier and a different trigonometric identity:

\sin \alpha \cos \beta = {\sin(\alpha - \beta) \over 2} + {\sin(\alpha + \beta) \over 2} \approx {\alpha - \beta \over 2} + {\sin(\alpha + \beta) \over 2}

The first term provides the desired phase difference. The second term is a sinusoid at twice the reference frequency, so it can be filtered out.

The presence of the sum frequency at the mixer output also adds complexity in applications where spectral purity of the VCO signal is important. This causes frequency modulation of the VCO at twice the reference frequency. The resulting unwanted (spurious) sidebands, also called "reference spurs" can dominate the filter requirements and reduce the capture range and lock time well below the requirements. In these applications the more complex digital phase detectors are used which do not have as severe a reference spur component on their output.

Both the quadrature and simple multiplier phase detectors have an output that depends on the input amplitudes as well as the phase difference. In practice, the input amplitudes are normalized.

When in lock, the steady-state phase difference at the inputs is near 90 degrees for these phase detectors. That's why sin(α) and cos(β) were used in the development above. The actual difference is determined by the DC loop gain.

Digital phase detector

An Example CMOS Digital Phase Frequency Detector ( Transistor Variety). Inputs are R and V while the outputs UP and DN feed to a charge pump.

The simplest is an XOR gate. It compares well to the analog mixer in that it locks near a 90° phase difference and has a square-wave output at twice the reference frequency. The average value of this square wave is the DC component that sets the VCO frequency. The square-wave changes duty-cycle in proportion to the phase difference resulting, after the filter, in the VCO control voltage. It requires inputs that are symmetrical square waves, or nearly so. The remainder of its characteristics are very similar to the analog mixer for capture range, lock time, reference spurious and low-pass filter requirements.

A more complex digital PD uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency and is known as a Phase Frequency Detector.

A PLL with a bang-bang charge pump phase detector supplies current pulses with fixed total charge, either positive or negative, to the capacitor acting as an integrator. A phase detector for a bang-bang charge pump must always have a dead band where the phases of the reference and feedback clocks are close enough that the detector fires either both or neither of the charge pumps, for no total effect. Bang-bang phase detectors are simple, but are associated with significant minimum peak-to-peak jitter, because once in lock the phase offset drifts inside the two extreme values of the dead band without triggering any corrections.

A proportional phase detector employs a charge pump that supplies charge amounts in proportion to the phase error detected. Some have dead bands and some do not. A dead band is an area where small changes in phase difference produce no correction to the VCO. Specifically, some designs produce both "up" and "down" control pulses even when the phase difference is zero. These pulses are small, nominally the same duration, and cause the charge pump to produce equal-charge positive and negative current pulses when the phase is perfectly matched. If the inputs are slightly mismatched, either the up or down pulse will contain slightly more charge than the other and the PLL will be able to correct the offset. PLLs with this kind of control system don't exhibit a dead band and typically have lower minimum peak-to-peak jitter that is determined by other limiting factors.

These types, having outputs consisting of very narrow pulses at lock, are very useful for applications requiring very low VCO spurious outputs. The narrow pulses contain very little energy and are easy to filter out of the VCO control voltage. This results in low VCO control line ripple and therefore low FM sidebands on the VCO.

It is frequently required to know when the loop is out of lock. The more complex digital phase-frequency detectors usually have an output that allows a reliable indication of an out of lock condition.

Filter

Oscillators

Inductive oscillators (LC oscillators) are built of an LC "tank" circuit, which oscillates by charging and discharging a capacitor through an inductor. These oscillators are typically used when a tunable precision frequency source is necessary, such as with radio transmitters and receivers. Most LC oscillators use off-chip inductors. On-chip inductors suffer large resistive losses, so that the Q of the resulting tank circuit is generally less than 10. As processes have made larger numbers of metal layers available (allowing designers to distance the inductor metal layer from the resistive substrate), on-chip inductors have become more useful.

A voltage-controlled capacitor is one method of making an LC oscillator vary its frequency in response to a control voltage. Any reverse-biased semiconductor diode displays a measure of voltage-dependent capacitance and can be used to change the frequency of an oscillator by varying a control voltage applied to the diodes. Special-purpose variable capacitance varactor diodes are available with well-characterized wide-ranging values of capacitance. Such devices are very convenient in the manufacture of voltage-controlled oscillators (a voltage-controlled inductor would be in principle as useful, but such devices are unsatisfactory at the frequencies usually desired).

Crystal oscillators are piezoelectric quartz crystals that mechanically vibrate between two slightly different shapes. Crystals have very high Q, and can only be tuned within a very small range of frequencies. Crystal oscillators are typically used as the frequency reference for PLLs, and can be found in nearly every consumer electronic device. Because the crystal is an off-chip component, it adds some cost and complexity to the system design, but the crystal itself is generally quite inexpensive.

Surface acoustic wave devices (SAWs) are a kind of crystal oscillator, but achieve much higher frequencies by establishing standing waves on the surface of the quartz crystal. These are more expensive than crystal oscillators, and are used in more specialized applications which require a direct and very accurate high frequency reference, for example, in cellular telephones.

For a PLL built into a microprocessor chip, ring oscillators can be used as voltage-controlled oscillators-a free running multivibrator (VCOs). They are built of a ring of active delay stages. Generally the ring has an odd number of inverting stages, so that there is no single stable state for the internal ring voltages. Instead, a single transition propagates endlessly around the ring. The frequency is controlled by varying either the supply voltage or the capacitive loading on each stage. VCOs generally have the lowest Q of the used oscillators, and so suffer more jitter than the other types. The jitter can be made low enough for many applications (such as driving an ASIC), in which case VCOs enjoy the advantages of having no off-chip components (expensive) or on-chip inductors (low yields on generic CMOS processes). These oscillators also have larger tuning ranges than the other kinds, which improves yield and is sometimes a feature of the end product (for instance, the dot clock on a graphics card which drives a wide range of monitors).

Digital PLLs use digital filtering techniques to process the baseband error signal. A time-to-digital converter is used in place of the analog phase detector to digitize the time arrival difference between the NCO output and a reference signal. The resulting digital signal is filtered using signal processing techniques before finally being converted back into the analog domain (via a digital-to-analog converter) to provide a steering signal to the analog VCO.[11]

Number controlled oscillators. Software PLL.

Feedback path and optional divider

An Example Digital Divider (by 4) for use in the Feedback Path of a Multiplying PLL

Most PLLs also include a divider between the oscillator and the feedback input to the phase detector to produce a frequency synthesizer. A programmable divider is particularly useful in radio transmitter applications, since a large number of transmit frequencies can be produced from a single stable, accurate, but expensive, quartz crystal–controlled reference oscillator.

Some PLLs also include a divider between the reference clock and the reference input to the phase detector. If this divider divides by M, it allows the VCO to multiply the reference frequency by N/M. It might seem simpler to just feed the PLL a lower frequency, but in some cases the reference frequency may be constrained by other issues, and then the reference divider is useful. Frequency multiplication in a sense can also be attained by locking the PLL to the 'N'th harmonic of the signal.

Modeling

Time domain model

The equations governing a phase-locked loop with an analog multiplier as the phase detector may be derived as follows. Let the input to the phase detector be x_c(t) and the output of the voltage-controlled oscillator (VCO) is x_r(t) with frequency \omega_r(t), then the output of the phase detector x_m(t) is given by

x_m(t) = x_c(t) \cdot x_r(t)

the VCO frequency may be written as a function of the VCO input y(t) as

\omega_r(t) = \omega_f + g_v y(t)\,

where g_v is the sensitivity of the VCO and is expressed in Hz / V.

Hence the VCO output takes the form

x_r(t) = A_r \cos\left( \int_0^t \omega_r(\tau)\, d\tau \right) = A_r \cos(\omega_f t + \varphi(t) )

where

\varphi(t) = \int_0^t g_v y(\tau)\, d\tau

The loop filter receives this signal as input and produces an output

x_{f}(t) = F_{{\rm filter}}(x_m(t))

where F_{{\rm Filter}} is the operator representing the loop filter transformation.

When the loop is closed, the output from the loop filter becomes the input to the VCO thus

y(t) = x_f(t) = F_{{\rm filter}}(x_m(t))

We can deduce how the PLL reacts to a sinusoidal input signal:

x_c(t) = A_c \sin(\omega_c t).

The output of the phase detector then is:

x_m(t) = A_c \sin( \omega_c t ) A_r \cos(\omega_f t + \varphi(t)).

This can be rewritten into sum and difference components using trigonometric identities:

x_m(t) = {A_c A_f \over 2} \sin( \omega_c t - \omega_f t - \varphi(t) ) + {A_c A_f \over 2} \sin( \omega_c t + \omega_f t + \varphi(t) )

As an approximation to the behaviour of the loop filter we may consider only the difference frequency being passed with no phase change, which enables us to derive a small-signal model of the phase-locked loop. If we can make \omega_f \approx \omega_c, then the \sin(\cdot) can be approximated by its argument resulting in: y(t)=x_f(t) \simeq - A_c A_f \varphi (t) / 2. The phase-locked loop is said to be locked if this is the case.[12]

Linearized phase domain model

Phase locked loops can also be analyzed as control systems by applying the Laplace transform. The loop response can be written as:

\frac{\theta_o}{\theta_i} = \frac{K_p K_v F(s)} {s + K_p K_v F(s)}

Where

The loop characteristics can be controlled by inserting different types of loop filters. The simplest filter is a one-pole RC circuit. The loop transfer function in this case is:

F(s) = \frac{1}{1 + s R C}

The loop response becomes:

\frac{\theta_o}{\theta_i} = \frac{\frac{K_p K_v}{R C}}{s^2 + \frac{s}{R C} + \frac{K_p K_v}{R C}}

This is the form of a classic harmonic oscillator. The denominator can be related to that of a second order system:

s^2 + 2 s \zeta \omega_n + \omega_n^2

Where

For the one-pole RC filter,

\omega_n = \sqrt{\frac{K_p K_v}{R C}}
\zeta = \frac{1}{2 \sqrt{K_p K_v R C}}

The loop natural frequency is a measure of the response time of the loop, and the damping factor is a measure of the overshoot and ringing. Ideally, the natural frequency should be high and the damping factor should be near 0.707 (critical damping). With a single pole filter, it is not possible to control the loop frequency and damping factor independently. For the case of critical damping,

R C = \frac{1}{2 K_p K_v}
\omega_c = K_p K_v \sqrt{2}

A slightly more effective filter, the lag-lead filter includes one pole and one zero. This can be realized with two resistors and one capacitor. The transfer function for this filter is

F(s) = \frac{1+s C R_2}{1+s C (R_1+R_2)}

This filter has two time constants

\tau_1 = C (R_1 + R_2)
\tau_2 = C R_2

Substituting above yields the following natural frequency and damping factor

\omega_n = \sqrt{\frac{K_p K_v}{\tau_1}}
\zeta = \frac{1}{2 \omega_n \tau_1} + \frac{\omega_n \tau_2}{2}

The loop filter components can be calculated independently for a given natural frequency and damping factor

\tau_1 = \frac{K_p K_v}{\omega_n^2}
\tau_2 = \frac{2 \zeta}{\omega_n} - \frac{1}{K_p K_v}

Real world loop filter design can be much more complex e.g. using higher order filters to reduce various types or source of phase noise. (See the D Banerjee ref below)

See also

References

  1. ↑ If the frequency is constant and the initial phase is zero, then the phase of a sinusoid is proportional to time.
  2. ↑ E. V. Appleton, Automatic synchronization of triode oscillators, Proc. Cambridge Phil. Soc., 21(Part III):231 (1922-1923)
  3. ↑ Henri de Bellescize, "La réception synchrone," L'Onde Électrique (later: Revue de l'Electricité et de l'Electronique), vol. 11, pages 230-240 (June 1932).
  4. ↑ See also: French patent no. 635,451 (filed: 6 October 1931; issued: 29 September 1932); and U.S. patent "Synchronizing system," no. 1,990,428 (filed: 29 September 1932; issued: 5 February 1935).
  5. ↑ Notes for a University of Guelph course describing the PLL and early history, including an IC PLL tutorial
  6. ↑ National Television Systems Committee Video Display Signal
  7. ↑ A. B. Grebene, H. R. Camenzind, “Phase Locking As A New Approach For Tuned Integrated Circuits”, ISSCC Digest of Technical Papers, pp. 100-101, Feb. 1969.
  8. ↑ TI SN74LS297, http://focus.ti.com/lit/an/sdla005b/sdla005b.pdf
  9. ↑ M Horowitz, C. Yang, S. Sidiropoulos (1998-01-01). "High-speed electrical signaling: overview and limitations". IEEE Micro. http://www-vlsi.stanford.edu/papers/mh_micro_98.pdf. 
  10. ↑ List of PLL Synthesizers/VCOs from Analog Devices
  11. ↑ http://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf
  12. ↑  This article incorporates public domain material from the General Services Administration document "Federal Standard 1037C" (in support of MIL-STD-188).