Itanium

Itanium

Itanium 2 processor
Produced	From mid 2001 to present
Common manufacturer(s)	Intel
Max. CPU clock rate	733 MHz to 1.73 GHz
FSB speeds	300 MHz to 667 MHz
Instruction set	Itanium
Cores	1, 2 or 4
Socket(s)	PAC611 PAC418 (original Itanium) LGA1248 (Itanium 9300 series)
Core name(s)	McKinley Madison Hondo Deerfield Montecito Montvale Tukwila

Itanium (pronounced /aɪˈteɪniəm/ eye-TAY-nee-əm) is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). The processors are marketed for use in enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel.

Intended to push performance beyond existing designs, Itanium departed dramatically from Intel's legacy x86 and other architectures. The Itanium architecture is based on explicit instruction-level parallelism, in which decisions about which instructions to execute in parallel must be made by the compiler. By contrast, other superscalar architectures depend on elaborate processor circuitry to keep track of instruction dependencies during runtime. Itanium cores up to and including Tukwila execute up to six instructions per clock cycle.

Putting aside a proposal to update the x86 architecture, Intel invested in a protracted development process. After many delays the first Itanium processor, codenamed Merced, was released in 2001. Although its speed would have been impressive if introduced on time in 1999, it ran only half as fast as the contemporary x86-based Pentium 4.^[1] HP produces most Itanium-based systems as part of its HP Integrity Servers line, but several other manufacturers also offer systems based on Itanium. As of 2008^[update], Itanium is the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, IBM POWER, and SPARC.^[2] The most recent processor, Tukwila, originally planned for release in 2007, was released on February 8, 2010.^[3][4]

Whilst initially targeted at high-end servers, Intel's long-term goal was to make Itanium the de facto standard 64-bit replacement for the aging x86 architecture in other markets. During the 2000s, however, AMD developed a 32-bit compatible 64-bit extension to x86 known as x86-64, later also adopted by Intel itself, which largely replaced 32-bit chips in most desktop and portable applications. Since high-end Itanium server implementations predominantly ran HP-UX as their operating system, this led to Microsoft announcing in April 2010 that it would not release any new versions of Windows on Itanium.^[5] Chips based on x86-64 were also scaled up to powerful multi-core 8 to 12 core processors, allowing them to be used in high-end server applications, casting some doubt even on Itanium's future in this area.

Contents 1 Market reception 1.1 High-end server market 1.2 Other markets 2 History 2.1 Development: 1989–2000 2.2 Itanium (Merced): 2001 2.3 Itanium 2: 2002–2010 2.4 Itanium 9300 (Tukwila) : 2010 3 Market share 4 Architecture 4.1 Instruction execution 4.2 Memory architecture 4.3 Architectural changes 5 Hardware support 5.1 Systems 5.2 Chipsets 6 Software support 7 Competition 8 Supercomputers and high-performance computing 9 Processors 9.1 Released processors 9.2 Future processors 9.2.1 Poulson 9.2.2 Kittson 10 Timeline 11 See also 12 References 13 External links

Market reception

High-end server market

When first released in 2001, Itanium's performance, compared to better established RISC and CISC processors, was disappointing.^[6][7] Emulation to run existing applications and operating systems was particularly poor, with one benchmark in 2001 reporting that it was equivalent at best to a 100 MHz Pentium in this mode.^[8] Itanium failed to make significant inroads, and also suffered from the successful introduction of x86-based systems into this market. Journalist John C. Dvorak, commenting in 2009 on the history of the Itanium processor, said "This continues to be one of the great fiascos of the last 50 years" in an article titled "How the Itanium Killed the Computer Industry".^[9] Tech columnist Ashlee Vance commented that the delays and underperformance "turned the product into a joke in the chip industry."^[10] In an interview, Donald Knuth said "The Itanium approach ... was supposed to be so terrific—until it turned out that the wished-for compilers were basically impossible to write."^[11] In late 2009 a former Intel official reported that the Itanium business had become profitable.^[12]

As of 2009 the chip is almost entirely deployed on servers made by HP, which have over 95% of the Itanium server market share,^[13] making the main operating system for Itanium HP-UX. Both Red Hat and Microsoft have announced plans to drop Itanium support in future versions of their operating systems due to lack of market interest.^[14][15]

Other markets

Although remaining in development, and having attained a limited success in the niche of high-end computing, Intel had originally hoped to make Itanium a replacement for the original x86 architecture.^[16]

AMD chose a different direction, designing the less radical x86-64, a 64-bit extension to the existing x86 architecture which Microsoft then put its support behind, forcing Intel to introduce the same extension to its own x86-based processors.^[17] These designs can run existing 32-bit applications at native hardware speed, while offering support for 64-bit memory addressing and other enhancements to new applications.^[13] This architecture has now become the predominant 64-bit architecture in the desktop and portable market; although some Itanium-based workstations were initially introduced by companies such as SGI, these are no longer available.

History

Development: 1989–2000

In 1989, HP determined that reduced instruction set computer (RISC) architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture, later named explicitly parallel instruction computing (EPIC), that allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, in which a single instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel.^[20] The goal of this approach is two-fold: to enable deeper inspection of the code to identify additional opportunities for parallel execution, and to simplify processor design and reduce energy consumption by eliminating the need for runtime scheduling circuitry.

HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998.^[20]

During development, Intel, HP, and industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computer (CISC) architectures for all general-purpose applications.^[6][7] Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures respectively in favor of migrating to IA-64.^[21]

Several groups developed operating systems for the architecture, including Microsoft Windows, Linux, and UNIX variants such as HP-UX, Solaris,^{[22] [23] [24]} Tru64 UNIX,^[21] and Monterey/64^[25] (the last three were canceled before reaching the market). By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, and the delivery of Merced began slipping.^[26] Technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches. There were also structural problems within the project, as the two parts of the joint team used different methodologies and had slightly different priorities. Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to. In addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more research was needed.

Intel announced the official name of the processor, Itanium, on October 4, 1999.^[27] Within hours, the name Itanic had been coined on a Usenet newsgroup, a reference to Titanic, the "unsinkable" ocean liner which sank in 1912.^[28] "Itanic" has since often been used by The Register,^[29] Scott McNealy,^[30] and others,^[31][32] to imply that the multibillion dollar investment in Itanium—and the early hype associated with it—would be followed by its relatively quick demise.

Itanium (Merced): 2001

Itanium (Merced)

Itanium processor
Produced	From June 2001 to June 2002
Common manufacturer(s)	Intel
Max. CPU clock rate	733 MHz to 800 MHz
FSB speeds	266 MT/s
Instruction set	Itanium
Cores	1
L2 cache	96 KiB
L3 cache	2 or 4 MiB
Socket(s)	PAC418
Core name(s)	Merced

By the time Itanium was released in June 2001, its performance was not superior to competing RISC and CISC processors.^[33] Itanium competed at the low-end (primarily 4-CPU and smaller systems) with servers based on x86 processors, and at the high end with IBM's POWER architecture and Sun Microsystems' SPARC architecture. Intel repositioned Itanium to focus on high-end business and HPC computing, attempting to duplicate x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing PA-RISC in HP systems, Alpha in Compaq systems and MIPS in SGI systems, though IBM also delivered a supercomputer based on this processor.^[34] POWER and SPARC remained strong, while the 32-bit x86 architecture continued to grow into the enterprise space. With economies of scale fueled by its enormous installed base, x86 has remained the preeminent "horizontal" architecture in enterprise computing.

Only a few thousand systems using the original Merced Itanium processor were sold, due to relatively poor performance, high cost and limited software availability.^[35] Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to market a year later.

Itanium processor family
Original logo	Version 2 logo	2006 logo	2008 logo	2009 new logo

Itanium 2: 2002–2010

Itanium 2

Itanium 2 processor
Produced	From 2002 to present
Designed by	Intel
Common manufacturer(s)	Intel
Max. CPU clock rate	900 MHz to 1.73 GHz
Instruction set	Itanium
Cores	1, 2 or 4
L2 cache	256 KiB on Itanium2 256 KiB(D) + 1MiB(I) or 512KiB(I) on (Itanium2 9x00 series)
L3 cache	1.5-24 MiB
Socket(s)	PAC611 FC-LGA6 (LGA1248) (Itanium 9300 series)
Core name(s)	McKinley Madison Hondo Deerfield Montecito Montvale Tukwila

The Itanium 2 processor was released in 2002, and was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium 2, code-named McKinley, was jointly developed by HP and Intel. It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem. McKinley contained 221 million transistors (of which 25 million were for logic), measured 19.5 mm by 21.6 mm (421 mm²) and was fabricated in a 180 nm, bulk CMOS process with six layers of aluminium metallization.^[36]

In 2003, AMD released the Opteron, which implemented its 64-bit architecture (x86-64). Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from x86. Intel responded by implementing x86-64 in its Xeon microprocessors in 2004.^[21]

Intel released a new Itanium 2 family member, codenamed Madison, in 2003. Madison used a 130 nm process and was the basis of all new Itanium processors until Montecito was released in June 2006.

In March 2005, Intel announced that it was working on a new Itanium processor, codenamed Tukwila, to be released in 2007. Tukwila would have four processor cores and would replace the Itanium bus with a new Common System Interface, which would also be used by a new Xeon processor.^[37] Later that year, Intel revised Tukwila's delivery date to late 2008.^[38]

In November 2005, the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate software porting.^[39] The Alliance announced that its members would invest $10 billion in Itanium solutions by the end of the decade.^[40]

In 2006, Intel delivered Montecito (marketed as the Itanium 2 9000 series), a dual-core processor that roughly doubled performance and decreased energy consumption by about 20 percent.^[41]

Intel released the Itanium 2 9100 series, codenamed Montvale, in November 2007.^[42] In May 2009 the schedule for Tukwila, its follow-on, was revised again, with release to OEMs planned for the first quarter of 2010.^[3]

Itanium 9300 (Tukwila) : 2010

The Itanium 9300 series processor, codenamed Tukwila, was released on 8 February 2010 with greater performance and memory capacity.^[4]

The device uses a 65 nm process, includes two to four cores, up to 24 MiB on-die caches, Hyper-Threading technology and integrated memory controllers. It implements double-device data correction, which helps to fix memory errors. Tukwila also implements Intel QuickPath Interconnect (QPI) to replace the Itanium bus-based architecture. It has a peak interprocessor bandwidth of 96 GB/s and a peak memory bandwidth of 34 GB/s. With QuickPath, the processor has integrated memory controllers and interfaces the memory directly, using QPI interfaces to directly connect to other processors and I/O hubs. QuickPath is also used on Intel processors using the Nehalem microarchitecture, making it probable that Tukwila and Nehalem will be able to use the same chipsets.^[43] Tukwila incorporates four memory controllers, each of which supports multiple DDR3 DIMMs via a separate memory controller,^[44] much like the upcoming Nehalem-based Xeon processor code-named Beckton.^[45]

Market share

In comparison with its Xeon family of server processors, Itanium has never been a high-volume product for Intel. Intel does not release production numbers. One industry analyst estimated that the production rate was 200,000 processors per year in 2007.^[46]

Please note that the following numbers are based on servers and not on processors. Neither is reported how many processors or multi core processors were built into these servers nor is it clear whether clustered servers were counted as a single server or not. Therefore there seems to be no valid method for reasonably determining how many processors are represented by that number of systems.

According to Gartner Inc., the total number of Itanium servers sold by all vendors in 2007 was about 55,000. This compares with 417,000 RISC servers (spread across all RISC vendors) and 8.4 million x86 servers. From 2001 through 2007, IDC reports that a total of 184,000 Itanium-based systems have been sold. For the combined POWER/SPARC/Itanium systems market, IDC reports that POWER captured 42% of revenue and SPARC captured 32%, while Itanium-based system revenue reached 26% in the second quarter of 2008.^[47] According to an IDC analyst, in 2007 HP accounted for perhaps 80% of Itanium systems revenue.^[48] According to Gartner, in 2008 HP accounted for 95% of Itanium sales.^[10] HP's Itanium system sales were at an annual rate of $4.4Bn at the end of 2008, and declined to $3.5Bn by the end of 2009,^[49] compared to a 35% decline in UNIX system revenue for Sun and an 11% drop for IBM, with an x86-64 server revenue increase of 14% during this period. Itanium customers may have deferred purchases to wait for the release of Tukwila-based systems.

Architecture

Intel Itanium Architecture

Designer	HP and Intel
Bits	64-bit
Introduced	2001
Design	EPIC
Type	Register-Register
Endianness	Selectable
Registers
128 64-bit general purpose registers 128 82-bit floating-point registers 64 1-bit predicate registers

Intel has extensively documented the Itanium instruction set and microarchitecture,^[50] and the technical press has provided overviews.^[6][26] The architecture has been renamed several times during its history. HP originally called it PA-WideWord. Intel later called it IA-64, then Itanium Processor Architecture (IPA),^[51] before settling on Intel Itanium Architecture, but it is still widely referred to as IA-64.

It is a 64-bit register-rich explicitly-parallel architecture. The base data word is 64 bits, byte-addressable. The logical address space is 2⁶⁴ bytes. The architecture implements predication, speculation, and branch prediction. It uses a hardware register renaming mechanism rather than simple register windowing for parameter passing. The same mechanism is also used to permit parallel execution of loops. Speculation, prediction, predication, and renaming are under control of the compiler: each instruction word includes extra bits for this. This approach is the distinguishing characteristic of the architecture.

The architecture implements 128 integer registers, 128 floating point registers, 64 one-bit predicates, and eight branch registers. The floating point registers are 82 bits long to preserve precision for intermediate results.

Instruction execution

Each 128-bit instruction word contains three instructions, and the fetch mechanism can read up to two instruction words per clock from the L1 cache into the pipeline. When the compiler can take maximum advantage of this, the processor can execute six instructions per clock cycle. The processor has thirty functional execution units in eleven groups. Each unit can execute a particular subset of the instruction set, and each unit executes at a rate of one instruction per cycle unless execution stalls waiting for data. While not all units in a group execute identical subsets of the instruction set, common instructions can be executed in multiple units.

The execution unit groups include:

• Six general-purpose ALUs, two integer units, one shift unit
• Four data cache units
• Six multimedia units, two parallel shift units, one parallel multiply, one population count
• Two 82-bit floating-point multiply-accumulate units, two SIMD floating-point multiply-accumulate units (two 32-bit operations each)^[52]
• Three branch units

The compiler can often group instructions into sets of six that can execute at the same time. Since the floating-point units implement a multiply-accumulate operation, a single floating point instruction can perform the work of two instructions when the application requires a multiply followed by an add: this is very common in scientific processing. When it occurs, the processor can execute four FLOPs per cycle. For example, the 800 MHz Itanium had a theoretical rating of 3.2 GFLOPS and the fastest Itanium 2, at 1.67 GHz, was rated at 6.67 GFLOPS.

Memory architecture

From 2002 to 2006, Itanium 2 processors shared a common cache hierarchy. They had 16 KiB of Level 1 instruction cache and 16 KiB of Level 1 data cache. The L2 cache was unified (both instruction and data) and is 256 KiB. The Level 3 cache was also unified and varied in size from 1.5 MiB to 24 MiB. The 256 KiB L2 cache contains sufficient logic to handle semaphore operations without disturbing the main arithmetic logic unit (ALU).

Main memory is accessed through a bus to an off-chip chipset. The Itanium 2 bus was initially called the McKinley bus, but is now usually referred to as the Itanium bus. The speed of the bus has increased steadily with new processor releases. The bus transfers 2×128 bits per clock cycle, so the 200 MHz McKinley bus transferred 6.4 GiB/s), and the 533 MHz Montecito bus transfers 17.056 GiB/s^[53]

Architectural changes

Itanium processors released prior to 2006 had hardware support for the IA-32 architecture to permit support for legacy server applications, but performance for IA-32 code was much worse than for native code and also worse than the performance of contemporaneous x86 processors. In 2005, Intel developed the IA-32 Execution Layer (IA-32 EL), a software emulator that provides better performance. With Montecito, Intel therefore eliminated hardware support for IA-32 code.

In 2006, with the release of Montecito, Intel made a number of enhancements to the basic processor architecture including:^[54]

• Hardware multithreading: Each processor core maintains context for two threads of execution. When one thread stalls during memory access, the other thread can execute. Intel calls this "coarse multithreading" to distinguish it from the "hyper-threading technology" Intel integrated into some x86 and x86-64 microprocessors. Coarse multithreading is well matched to the Intel Itanium Architecture and results in an appreciable performance gain.
• Hardware support for virtualization: Intel added Intel Virtualization Technology (Intel VT-i), which provides hardware assists for core virtualization functions. Virtualization allows a software "hypervisor" to run multiple operating system instances on the processor concurrently.
• Cache enhancements: Montecito added a split L2 cache, which included a dedicated 1 MiB L2 cache for instructions. The original 256 KiB L2 cache was converted to a dedicated data cache. Montecito also included up to 12 MiB of on-die L3 cache.

Hardware support

Systems

Server manufacturers' Itanium products

Company			latest product
name	from	to	name	CPUs
Compaq	2001	2001	Proliant 590	1–4
IBM	2001	2005	x455	1–16
Dell	2001	2005	PowerEdge 7250	1–4
Unisys	2002	2009	ES7000/one	1–32
HP	2001	now	Integrity	1–128
SGI	2001	now	Altix 4000	1–2048
Hitachi	2001	now	BladeSymphony 1000	1–8
Bull	2002	now	NovaScale	1–32
NEC	2002	now	Express5800 /1000	1–32
Fujitsu	2005	now	PRIMEQUEST	1–32

As of 2009^[update] several manufacturers offer Itanium systems, including HP, SGI, NEC, Fujitsu, Hitachi, and Groupe Bull. In addition, Intel offers a chassis that can be used by system integrators to build Itanium systems.^[55] HP, the only one of the industry's top four server manufacturers to offer Itanium-based systems today, manufactures at least 80% of all Itanium systems. HP sold 7200 systems in the first quarter of 2006.^[56] The bulk of systems sold are enterprise servers and machines for large-scale technical computing, with an average selling price per system in excess of US$200,000. A typical system uses eight or more Itanium processors.

Chipsets

The Itanium bus interfaces to the rest of the system via a chipset. Enterprise server manufacturers differentiate their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers. The chipset is the heart of the system-level architecture for each system design. Development of a chipset costs tens of millions of dollars and represents a major commitment to the use of the Itanium. IBM created a chipset in 2003, and Intel in 2002, but neither of them has developed chipsets to support newer technologies such as DDR2 or PCI Express.^[57] Currently, modern chipsets for Itanium supporting such technologies are manufactured by HP, Fujitsu, SGI, NEC, and Hitachi.

The "Tukwila" Itanium processor model has been designed to share a common chipset with the Intel Xeon processor EX (Intel’s Xeon processor designed for four processor and larger servers). The goal is to streamline system development and reduce costs for server OEMs, many of whom develop both Itanium- and Xeon-based servers.

Software support

As of 2010^[update] Itanium is supported by Windows Server 2003 and Windows Server 2008, multiple GNU/Linux distributions (including Debian, Ubuntu, Gentoo, Red Hat and Novell SuSE), FreeBSD,^[58] and HP-UX, OpenVMS, and NonStop from HP, all natively. However, Windows Server 2008 R2 will be the last version of Windows Server to support the Itanium and Red Hat Enterprise Linux 5 will be the last version to support the Itanium.^[14][15] Likewise, Canonical's Ubuntu 10.04 LTS will be the last supported Ubuntu on Itanium.^[59] Itanium is also supported by the mainframe environment GCOS from Groupe Bull and several IA-32 operating systems via Instruction Set Simulators.

HP will not be supporting or certifying Linux on Itanium 9300 (Tukwila) servers.^[60]

HP sells a virtualization technology for Itanium called Integrity Virtual Machines.

In order to allow more software to run on the Itanium, Intel supported the development of compilers optimized for the platform, especially its own suite of compilers.^[61][62] GCC,^[63][64] Open64 and MS Visual Studio 2005 (and later)^[65] are also able to produce machine code for Itanium. According to the Itanium Solutions Alliance over 13,000 applications were available for Itanium based systems in early 2008,^[66] though Sun has contested Itanium application counts in the past.^[67] The ISA also supports Gelato, an Itanium HPC user group and developer community that ports and supports open source software for Itanium.^[68]

Using QuickTransit, application binary software for IRIX/MIPS and Solaris/SPARC can run via "dynamic binary translation" on Linux/Itanium.

Competition

The Itanium 2 competes in the enterprise server and high-performance computing (HPC) markets. Itanium's major competitors include Sun Microsystems' UltraSPARC IV+, Fujitsu's SPARC64 VII and IBM's POWER6. The highest volume of 64-bit processors are the x86-64 based AMD Opteron and Intel Xeon lines. As of 2009^[update], most PCs were being shipped with x86-64 processors, but running with 32-bit operating systems.^[69]

In 2005, Itanium systems accounted for about 14% of HPC systems revenue, but the percentage has declined as the industry shifts to x86-64 clusters for this application.^[70]

An October 2008 paper by Gartner on the Tukwila processor stated that "...the future roadmap for Itanium looks as strong as that of any RISC peer like Power or SPARC."^[71]

Supercomputers and high-performance computing

An Itanium-based computer first appeared on list of the TOP500 supercomputers in November 2001.^[34] The best position ever achieved by an Itanium 2 based system in the list was #2, achieved in June 2004, when Thunder (LLNL) entered the list with an Rmax of 19.94 Teraflops. In November 2004, Columbia entered the list at #2 with 51.8 Teraflops, and there was at least one Itanium-based computer in the top 10 from then until June 2007. The peak number of Itanium-based machines on the list occurred in the November 2004 list, at 84 systems (16.8%); by June 2010, this had dropped to five systems (1%).^[72]

Processors

Released processors

The Itanium processors show a progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130 nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90 nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and front-side bus frequency of up to 667 MHz.

Codename	process	Released	Clock	L2 Cache/ core	L3 Cache/ core	Bus	dies/ device	cores/ die	watts/ device	Comments
Itanium
Merced	180 nm	2001-06	733 MHz	96 KiB	none	266 MHz	1	1	116	2 MiB off-die L3 cache
			800 MHz						130	4 MiB off-die L3 cache
Itanium 2
McKinley	180 nm	2002-07-08	900 MHz	256 KiB	1.5 MiB	400 MHz	1	1	130	HW branchlong
			1 GHz		3 MiB				130
Madison	130 nm	2003-06-30	1.3 GHz		3 MiB				130
			1.4 GHz		4 MiB				130
			1.5 GHz		6 MiB				130
		2003-09-08	1.4 GHz		1.5 MiB				130
		2004-04	1.4 GHz		3 MiB				130
			1.6 GHz
Deerfield		2003-09-08	1.0 GHz		1.5 MiB				62	Low voltage
Hondo[73]		2004-Q1	1.1 GHz		4 MiB	400 MHz	2	1	260	32 MiB L4
Fanwood		2004-11-08	1.6 GHz		3 MiB	533 MHz	1	1	130
			1.3 GHz			400 MHz			62?	Low voltage
Madison		2004-11-08	1.6 GHz		9 MiB	400 MHz			130
		2005-07-05	1.67 GHz		6 MiB	667 MHz			130
		2005-07-18	1.67 GHz		9 MiB	667 MHz			130
Itanium 2 9000 series
Montecito	90 nm	2006-07-18	1.4 GHz	256 KiB (D)+ 1 MiB (I)	6-24 MiB	400 MHz	1	2	104	Virtualization, Multithread, no HW IA-32
			1.6 GHz			533 MHz
Itanium 2 9100 series
Montvale	90 nm	2007-10-31	1.42–1.66 GHz	256 KiB (D)+ 1 MiB (I)	8-24 MiB	400–667 MHz	1	1–2	75–104	Core-level lockstep, demand-based switching
Itanium 9300 series
Tukwila	65 nm	2010-02-08	1.33-1.73 GHz	256 KiB (D)+ 512 KiB (I)	10-24 MiB	QPI with a speed of 4.8 GT/s	1	2–4	130–185	A new point-to-point processor interconnect, the QPI, replacing the FSB. Turbo Boost

Future processors

As of December 2009^[update], some information and speculations on future Itanium processors and roadmaps have been released.

Poulson

Poulson will be the follow-on processor to Tukwila and is planned for release in 2012.^[74] According to Intel, it will skip the 45 nm process technology and use a 32 nm process technology; it will feature eight or more cores, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization.^[43]

Kittson

Kittson will follow Poulson in 2014. Few details are known other than the existence of the codename and the binary and socket compatibility between Poulson, Kittson and Tukwila.^[43]

Timeline

• 1989:
  • HP begins investigating EPIC^[20]
• 1994:
  • June: HP and Intel announce partnership^[75]
• 1995:
  • September: HP, Novell, and SCO announce plans for a "high volume UNIX operating system" to deliver "64-bit networked computing on the HP/Intel architecture"^[76]
• 1996:
  • October: Compaq announces it will use IA-64^[77]
• 1997:
  • June: IDC predicts IA-64 systems sales will reach $38bn/yr by 2001^[18]
  • October: Dell announces it will use IA-64^[78]
  • December: Intel and Sun announce joint effort to port Solaris to IA-64^[22][23][24]
• 1998:
  • March: SCO admits HP/SCO Unix alliance is now dead
  • June: IDC predicts IA-64 systems sales will reach $30bn/yr by 2001^[18]
  • June: Intel announces Merced will be delayed, from second half of 1999 to first half of 2000^[79]
  • September: IBM announces it will build Merced-based machines^[80]
  • October: Project Monterey is formed to create a common UNIX for IA-64
• 1999:
  • February: Project Trillian is formed to port Linux to IA-64
  • August: IDC predicts IA-64 systems sales will reach $25bn/yr by 2002^[18]
  • October: Intel announces the Itanium name
  • October: the term Itanic is first used in The Register^[29]

• 2000:
  • February: Project Trillian delivers source code
  • June: IDC predicts Itanium systems sales will reach $25bn/yr by 2003^[18]
  • July: Sun and Intel drop Solaris-on-Itanium plans^[81]
  • August: AMD releases specification for x86-64, a set of 64-bit extensions to Intel's own x86 architecture intended to compete with IA-64. It will eventually market this under the name "AMD64"
• 2001:
  • June: IDC predicts Itanium systems sales will reach $15bn/yr by 2004^[18]
  • June: Project Monterey dies
  • July: Itanium is released
  • October: IDC predicts Itanium systems sales will reach $12bn/yr by the end of 2004^[18]
  • November: IBM's 320-processor Titan NOW Cluster at National Center for Supercomputing Applications is listed on the TOP500 list at position #34^[34]
  • November: Compaq delays Itanium Product release due to problems with processor^[82]
  • December: Gelato is formed
• 2002:
  • March: IDC predicts Itanium systems sales will reach $5bn/yr by end 2004^[18]
  • June: Itanium 2 is released
• 2003:
  • April: IDC predicts Itanium systems sales will reach $9bn/yr by end 2007^[18]
  • April: AMD releases Opteron, the first processor with x86-64 extensions
  • June: Intel releases the "Madison" Itanium 2
• 2004:
  • February: Intel announces it has been working on its own x86-64 implementation (which it will eventually market under the name "Intel 64")
  • June: Intel releases its first processor with x86-64 extensions, a Xeon processor codenamed "Nocona"
  • June: Thunder, a system at LLNL with 4096 Itanium 2 processors, is listed on the TOP500 list at position #2^[83]
  • November: Columbia, an SGI Altix 3700 with 10160 Itanium 2 processors at NASA Ames Research Center, is listed on the TOP500 list at position #2.^[84]
  • December: Itanium system sales for 2004 reach $1.4bn
• 2005:
  • January: HP ports OpenVMS to Itanium^[85]
  • February: IBM server design drops Itanium support^[57][86]
  • June: An Itanium 2 sets a record SPECfp2000 result of 2,801^[87] in a Hitachi, Ltd. Computing blade.
  • September: Itanium Solutions Alliance is formed^[88]
  • September: Dell exits the Itanium business^[89]
  • October: Itanium server sales reach $619M/quarter in the third quarter.
  • October: Intel announces one-year delays for Montecito, Montvale, and Tukwila^[38]
• 2006:
  • January: Itanium Solutions Alliance announces a $10bn collective investment in Itanium by 2010
  • February: IDC predicts Itanium systems sales will reach $6.6bn/yr by 2009^[19]
  • June: Intel releases the dual-core "Montecito" Itanium 2 9000 series^[90]
• 2007:
  • October: Intel releases the "Montvale" Itanium 2 9100 series.
  • November: Intel renames the family from Itanium 2 back to Itanium.
• 2009:
  • December: Red Hat announces that it is dropping support for Itanium in the next release of its enterprise OS, Red Hat Enterprise Linux 6.
• 2010:
  • February: Intel announces the "Tukwila" Itanium 9300 series.^[4]
  • April: Microsoft announces phase-out of support for Itanium.^[91]

See also

• List of Intel Itanium microprocessors

References

External links

• Intel Itanium Home Page
• HP Integrity Servers Home Page
• Intel Itanium Specifications
• Some undocumented Itanium 2 microarchitectural information
• IA-64 tutorial, including code examples
• Itanium Docs at HP

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