Image:X86 Paging PAE 4K.svg

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X86_Paging_PAE_4K.svg‎ (SVG file, nominally 621 × 396 pixels, file size: 20 KB)

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[edit] Beschreibung

Description
Deutsch: Schematische Darstellung der Umsetzung von linearen in physische Adressen bei x86-kompatiblen CPUs im 32-Bit Protected Mode. Seitengröße: 4 KiByte, mit PAE.
English: Schematic drawing of translation of linear to physical addresses in 32 bit protected mode. Page size: 4 KiByte, PAE enabled
Source

eigene Arbeit / own work using Xfig.
Date

2008-03-20
Author

RokerHRO
Permission
(Reusing this image)

see below
Other versions See http://roker.dingens.org/wikipedia/fig/ for original .fig file.

[edit] Licensing:

I, the copyright holder of this work, hereby publish it under the following licenses:
GNU head Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation license, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation license".

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File history

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Date/TimeDimensionsUserComment
current11:49, 20 March 2008621×396 (20 KB)RokerHRO ({{Information |Description={{de|Schematische Darstellung der Umsetzung von linearen in physische Adressen bei x86-kompatiblen CPUs im 32-Bit Protected Mode. Seitengröße: 4 KiByte, mit PAE.}} {{en|Schematic drawing of translation of linear to physical ad)
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