Image:Wishbone shared bus.jpg
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[edit] Summary
Source: 'WISHBONE System-on-Chip (SoC)Interconnection Architecture for Portable IP Cores', Revision: B.3, Released: September 7, 2002, wbspec_b3.pdf.
Page 3 of the spec states that: "Notice is hereby given that this document is not copyrighted, and has been placed into the public domain. It may be freely copied and distributed by any means."
[edit] Licensing
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Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. |
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| Date/Time | Dimensions | User | Comment | |
|---|---|---|---|---|
| current | 20:40, 18 November 2007 | 598×151 (14 KB) | Eeinfo2008 (Talk | contribs) | (Source: 'WISHBONE System-on-Chip (SoC)Interconnection Architecture for Portable IP Cores', Revision: B.3, Released: September 7, 2002, [http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf wbspec_b3.pdf]. Page 3 of the spec states that: "Noti) |
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