WDC 65C02
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The Western Design Center WDC 65C02 microprocessor is an upgraded CMOS version of the popular NMOS-based MOS Technology 6502 8-bit CPU — the CMOS redesign being made by Bill Mensch of the Western Design Center (WDC). Over various periods of time, the 65C02 has been second-sourced by NCR, GTE, Rockwell, Synertek and Sanyo.
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[edit] Introduction and features
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It has been suggested that W65C02S be merged into this article or section. (Discuss) |
The W65C02S is a low-power general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. It is a fully static core which allows the primary clock to be slowed down indefinitely or fully stopped in either the high or low state. The variable length instruction set and manually optimized core size are intended to make the W65C02S be well suited for low power system-on-chip (SoC) designs.
WDC makes a Verilog hardware description model available for designing the 65C02 core into ASICs and FPGAs. As is common in the semiconductor industry, the company also provides a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.
[edit] General logic features
- 8-bit data bus
- 16-bit address bus (providing an address space of 64K bytes)
- 8-bit arithmetic logic unit (ALU)
- 8-bit processor registers:
- 16-bit program counter
- 69 instructions, implemented by 212 operation codes
- 16 addressing modes, including zero page addressing
[edit] Logic specifics
- Vector Pull (VPB) output indicates when interrupt vectors are being addressed
- WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external events
[edit] Electrical features
- Operating voltage range specified at 1.8/2.5/3.0/3.3/5.0 V ±5%
- Power consumption of 150uA @ 1 MHz
- Variable length instruction set, enabling code size optimization over fixed length instruction set processors, which also results in power savings
- Fully static circuitry allows stopping the clock to conserve power
[edit] Comparison with the MOS 6502
[edit] Instruction set
The 65C02 shares its predecessor's 8-bit instruction set architecture and 16-bit memory addressing, but adds a number of improvements and documented opcodes, the most useful being instructions that can push or pull the .X and .Y index registers to/from the stack. Undefined opcodes have been converted into NOPs, although of varying instruction lengths.
Significantly, the defective "indirect jump page wrap" instruction (JMP (<ADDR>), where <ADDR> straddles a memory page boundary) has been fixed, eliminating a constant source of trouble for unwary assembly language programmers. This instruction has also been enhanced with .X register indexing, making it possible to code JMP (<ADDR>,X), enabling the development of a simple jump table management methodology.
Some variants of the 65C02 (including the WDC W65C02S and the Rockwell R65C00 family) feature individual bit manipulation operations (RMB, SMB, BBR and BBS). The 65SC02 was also available, which lacked these operations.
[edit] Status register
Other problems with the 6502, fixed in the 65C02, relate to its program status register, which contains eight system flags. Some flags are set or reset under program control. Others reflect the status of the machine after arithmetic or bit manipulation instructions.
| N | -- | Negative result |
| V | -- | Sign bit overflow |
| 1 | -- | Undefined (always set) |
| B | -- | Break flag (set by BRK instruction) |
| D | -- | Decimal mode enabled |
| I | -- | IRQ disabled |
| Z | -- | Zero result |
| C | -- | Arithmetic carry (borrow) |
In all NMOS logic forms of the 6502, the decimal flag (D flag) is not initialized to a known state following reset or when an interrupt is processed, which may lead to arbitrary behavior. This forces 6502 programmers to use the CLD instruction early in the reset handler code (it is generally the second instruction executed after SEI), as well as in the front end of the interrupt handler. The 65C02 addresses these problems by causing the D flag to be cleared at reset or upon receipt of an interrupt (after the status register is push on to the stack.
Also, in NMOS 6502s, the N flag is invalid when the processor is operating in decimal mode. The 65C02 fixes this problem (at the cost of an additional clock cycle), and thus increases the usefulness of decimal mode.
[edit] Notable uses of the 65C02
[edit] Home computers
- Apple IIc portable improved Apple II, by Apple Computer
- Apple Enhanced IIe by Apple Computer
- BBC Master home/educational computer, by Acorn Computers Ltd (65SC12 plus optional 65C102)
- Replica I by Briel Computers, a replica of the Apple I hobbyist computer
[edit] Video game consoles
- Atari Lynx handheld (65SC02 @ 4 MHz)
- TurboGrafx-16 aka PC Engine (HuC6280 @ 1.78 MHz and 7.16 MHz), by NEC
- GameKing handhelds (6 MHz), by Time Top
- Watara Supervision handhelds (65SC02 @ 4 MHz)
[edit] Other products
- TurboMaster accelerator cartridge for the Commodore 64 home computer (up to 4× speedup)
- mephisto MMV chess computer (4–20 MHz)
[edit] External links
- W65C02S 8–bit Microprocessor – Resource page at WDC's 65xx.com website
- The 6502/65C02/65C816 Instruction Set Decoded – From Neil Parker's Apple II page
- CPU World
| 65xx-series CPUs from MOS Technology, second source/clone vendors, and the Western Design Center |
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MOS 4510 ● MOS 6501 ● MOS 6502 ● WDC 65C02 ● Hudson HuC6280 ● Ricoh 2A03 ● MOS 6507 ● MOS 6508 ● MOS 6509 |
