Turion Ultra
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This article contains information about scheduled or expected future computer chips. It may contain preliminary or speculative information, and may not reflect the final specification of the product. |
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The Turion Ultra (codenamed Griffin) is the first processor family from AMD solely for the mobile platform, based on the Athlon 64 (K8) architecture with some specific architectural enhancements similar to current Phenom processors aimed at lower power consumption and longer battery life. The Turion Ultra processor was released as part of the "Puma" mobile platform in June 2008.
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[edit] Features
The Turion Ultra is a dual-core processor to be fabricated on 65 nm technology using 300 mm SOI wafers. It will support DDR2-800 SO-DIMM's and features a DRAM prefetcher to improve performance and a mobile-enhanced northbridge (memory controller, HyperTransport controller, and crossbar switch). Each processor core comes with 1 MiB L2 cache for a total of 2 MiB L2 cache for the entire processor. This is double the L2 cache found on the current Turion 64 X2 processor. Clock rates will range from 2.0 GHz to 2.4 GHz, and total design power (TDP) will range from 32 watts to 35 watts.[1]
An outstanding feature of the Turion Ultra processor is that it implements three voltage planes: one for the northbridge and one for each core.[2] This, along with multiple phase-locked loops (PLL), allows one core to alter its voltage and operating frequency independently of the other core, and independently of the northbridge. Indeed, in a matter of microseconds, the processor can switch to one of 8 frequency levels and one of 5 voltage levels. By adjusting frequency and voltage during use, the processor can adapt to different workloads and help reduce power consumption. It can operate as low as 250 MHz to conserve power during light use.
Additionally, the processor features deep sleep state C3, deeper sleep state C4 (AltVID), and HyperTransport 3.0 up to 2.6 GHz, or up to 41.6 GB/s bandwidth per link at 16-bit link width and dynamic scaling of HT link width down to 0-bit ("disconnected") in both directions from and to the chipset for four different usage scenarios [3]. It also implements multiple on-die thermal sensors through integrated SMBUS (SB-TSI) interface (replaces and eliminates the thermal monitor circuit chip through SMBUS in its predecessors) with additional MEMHOT signal sent from embedded controller to the processor, and reduces memory temperature.
The Turion Ultra processor will share the same socket S1 as its predecessor (Turion 64 X2) but will not have the same pinout.[4] It is designed to work with the RS780M chipset.
It is worth noting that given the above enhancements on the architecture, the cores were minimally modified and are based on the K8 instead of the K10 microarchitecture.[4] AMD Fellow Maurice Steinman has said the cores are almost transistor-for-transistor identical to those found in the 65 nm Turion 64 X2 processors[citation needed]. This makes it more likely that Turion Ultra will avoid the clock rate scaling difficulties present in AMD's K10 products.
[edit] Cores
[edit] Lion (65 nm SOI)
- Dual AMD64 core
- L1 cache: 64 + 64 KiB (data + instructions) per core
- L2 cache: 1 MiB per core, fullspeed
- Memory controller: dual channel DDR2-800 MHz
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, PowerNow!, NX bit, AMD-V
- Socket S1, HyperTransport (1800 MHz, 3600 MT/s, 12.8 GB/s CPU-RAM + 14.4 GB/s CPU-I/O transfer rate)
- Power consumption (TDP): 32, 35 watt max
- First release: June 4, 2008
- Clock rate: 2100, 2200, 2400 MHz
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[edit] External links
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