TILE64

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TILE64 Central processing unit
Produced:	2007
Manufacturer:	Tilera
Max CPU clock:	600 MHz to 900 MHz
Min feature size:	0.045 µm to 0.09 µm
Cores:	64

TILE64 is a microcontroller manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor.

The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches and a L3 cache that is considered an aggregate of all the L2 caches.^[1] A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system.

TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz.

Scheme of the TILE64 Processor

Scheme of a TILE of the TILE64 Processor

According to CTO and co-founder Anant Agarwal, Tilera will target the chip at networking equipment and digital video markets where the demands for computing processing are high.^[2]