TI MSP430

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The MSP430 is a microcontroller family from Texas Instruments. Built around a 16-bit CPU, the MSP430 is designed for low cost, low power consumption embedded applications. The architecture is reminiscent of the DEC PDP-11. The MSP430 is particularly well suited for wireless RF or battery powered applications.

The device comes in a variety of configurations featuring the usual peripherals: internal oscillator, timer including PWM, watchdog, USART, SPI, I2C, 10/12/14/16-bit ADCs, and brownout reset circuitry. Some less usual peripheral options include comparators (that can be used with the timers to do simple ADC), on-chip op-amps for signal conditioning, 12-bit DAC, LCD driver, hardware multiplier, and DMA for ADC results. Apart from some older EPROM (PMS430E3xx) and high volume mask ROM (MSP430Cxxx) versions, all of the devices are in-system programmable via JTAG or a built in bootstrap loader (BSL) using RS-232.

The MSP430 is a popular choice for low powered measurement devices. The current drawn in idle mode can be less than 1 microamp. The top CPU speed is 16 MHz. It can be throttled back for lower power consumption. Note that MHz is not equivalent to MIPS, and there are more efficient architectures that obtain higher MIPS rates at lower CPU clock frequencies, which can result in lower dynamic power consumption for an equivalent amount of processing.

There are, however, limitations that prevent it from being used in more complex embedded systems. The MSP430 does not have an external memory bus, so is limited to on-chip memory (up to 120 KB Flash and 10 KB RAM) which might be too small for applications that require large buffers or data tables.

Contents

[edit] MSP430 CPU

The MSP430 CPU uses a von Neumann architecture, with a single address space for instructions and data. Memory is byte-addressed, and pairs of bytes are combined little-endian to make 16-bit words.

The processor contains 16 16-bit registers. R0 is the program counter, R1 is the stack pointer, R2 is the status register, and R3 is a special register called the constant generator, providing access to 6 commonly used constant values without requiring an additional operand. R4 through R15 are available for general use.

The instruction set is very simple; there are 27 instructions in three families. Most instructions are available in 8-bit (byte) and 16-bit (word) versions, depending on the value of a B/W bit - the bit is set to 1 for 8-bit and 0 for 16-bit. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.

MSP430 instruction set
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction
0 0 0 1 0 0 opcode B/W As register Single-operand arithmetic
0 0 0 1 0 0 0 0 0 B/W As register RRC Rotate right through carry
0 0 0 1 0 0 0 0 1 0 As register SWPB Swap bytes
0 0 0 1 0 0 0 1 0 B/W As register RRA Rotate right arithmetic
0 0 0 1 0 0 0 1 1 0 As register SXT Sign extend byte to word
0 0 0 1 0 0 1 0 0 B/W As register PUSH Push value onto stack
0 0 0 1 0 0 1 0 1 0 As register CALL Subroutine call; push PC and move source to PC
0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 RETI Return from interrupt; pop SR then pop PC
0 0 1 condition 10-bit signed offset Conditional jump; PC = PC + 2×offset
0 0 1 0 0 0 10-bit signed offset JNE/JNZ Jump if not equal/zero
0 0 1 0 0 1 10-bit signed offset JEQ/JZ Jump if equal/zero
0 0 1 0 1 0 10-bit signed offset JNC/JLO Jump if no carry/lower
0 0 1 0 1 1 10-bit signed offset JC/JHS Jump if carry/higher or same
0 0 1 1 0 0 10-bit signed offset JN Jump if negative
0 0 1 1 0 1 10-bit signed offset JGE Jump if greater or equal
0 0 1 1 1 0 10-bit signed offset JL Jump if less
0 0 1 1 1 1 10-bit signed offset JMP Jump (unconditionally)
opcode source Ad B/W As destination Two-operand arithmetic
0 1 0 0 source Ad B/W As destination MOV Move source to destination
0 1 0 1 source Ad B/W As destination ADD Add source to destination
0 1 1 0 source Ad B/W As destination ADDC Add source and carry to destination
0 1 1 1 source Ad B/W As destination SUBC Subtract source from destination (with carry)
1 0 0 0 source Ad B/W As destination SUB Subtract source from destination
1 0 0 1 source Ad B/W As destination CMP Compare (pretend to subtract) source from destination
1 0 1 0 source Ad B/W As destination DADD Decimal add source to destination (with carry)
1 0 1 1 source Ad B/W As destination BIT Test bits of source AND destination
1 1 0 0 source Ad B/W As destination BIC Bit clear (dest &= ~src)
1 1 0 1 source Ad B/W As destination BIS Bit set (logical OR)
1 1 1 0 source Ad B/W As destination XOR Exclusive or source with destination
1 1 1 1 source Ad B/W As destination AND Logical AND source with destination (dest &= src)

Instructions are 16 bits, followed by up to two 16-bit extension words. There are four addressing modes, specified by the 2-bit As field. Some special versions can be constructed using R0, and modes other than register direct using R2 (the status register) and R3 (the constant generator) are interpreted specially.

Indexed addressing modes add a 16-bit extension word to the instruction.

MSP430 addressing modes
As Register Syntax Description
00 n Rn Register direct. The operand is the contents of Rn.
01 n x(Rn) Indexed. The operand is in memory at address Rn+x.
10 n @Rn Register indirect. The operand is in memory at the address held in Rn.
11 n @Rn+ Indirect autoincrement. As above, then the register is incremented by 1 or 2.
Addressing modes using R0 (PC)
01 0 (PC) LABEL Symbolic. x(PC) The operand is in memory at address PC+x.
11 0 (PC) #x Immediate. @PC+ The operand is the next word in the instruction stream.
Addressing modes using R2 (SP) and R3 (CG), special-case decoding
01 2 (SR) &LABEL Absolute. The operand is in memory at address x.
10 2 (SR) #4 Constant. The operand is the constant 4.
11 2 (SR) #8 Constant. The operand is the constant 8.
00 3 (CG) #0 Constant. The operand is the constant 0.
01 3 (CG) #1 Constant. The operand is the constant 1. There is no index word.
10 3 (CG) #2 Constant. The operand is the constant 2.
11 3 (CG) #-1 Constant. The operand is the constant -1.

Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.

Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC. In the two-operand instructions, there is only one Ad bit to specify the destination addressing mode, so only modes 00 (register direct) and 01 (indexed) are allowed. If both source and destination are indexed, the source extension word comes first.

When R0 (PC) or R1 (SP) are used with the autoincrement addressing mode, they are always incremented by two. Other registers (R4 through R15) are incremented by the operand size, either 1 or 2 bytes.

The status register contains 4 arithmetic status bits, a global interrupt enable, and 4 bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.

[edit] MSP430 address space

The general layout of the MSP430 address space is:

0x0000–0x0007 
Processor special function registers (interrupt control registers)
0x0008–0x00FF 
8-bit peripherals. These must be accessed using 8-bit loads and stores.
0x0100–0x01FF 
16-bit peripherals. These must be accessed using 16-bit loads and stores.
0x0200–0x09FF 
Up to 2048 bytes of RAM.
0x0C00–0x0FFF 
1024 bytes of bootstrap loader ROM (flash ROM parts only).
0x1000-0x1100 
256 bytes of data flash ROM (flash ROM parts only).
0x1100–0x38FF 
Extended RAM on models with more than 2048 bytes of RAM. (0x1100–0x18FF is a copy of 0x0200–0x09FF)
0x1100–0xFFFF 
Up to 60 kilobytes of program ROM. Smaller ROMs start at higher addresses. The last 16 or 32 bytes are interrupt vectors.

A few models include more than 2048 bytes of RAM; in that case RAM begins at 0x1100. The first 2048 bytes (0x1100–0x18FF) is mirrored at 0x0200–0x09FF for compatibility. Also, some recent models bend the 8-bit and 16-bit peripheral rules, allowing 16-bit access to peripherals in the 8-bit peripheral address range.

There is a new extended version of the architecture (called MSP430X) which allows a 20-bit address space. It allows additional program ROM beginning at 0x10000.

[edit] MSP430 families

There are four general families of MSP430 processors. In order of development, they were the '3xx family, the '1xx family, the '4xx family, and the '2xx family. The digit after the family identifies the model (generally higher model numbers are larger and more capable), the third digit identifies the amount of memory on board, and the fourth, if present, identifies a minor model variant. The most common variation is a different on-chip analog-to-digital converter.

MSP430x1xx 
This is the basic family without an embedded LCD controller. They are generally smaller than the '3xx family.
MSP430F2xx 
These are similar to the '1xx family, but operate at even lower power, support up to 16 MHz operation (all other families are limited to 8 MHz), and have a more accurate (+/-2%) on-chip clock that makes it easier to operate without an external crystal.
MSP430x3xx 
This is oldest family, designed for portable instrumentation with an embedded LCD controller. This also includes a frequency-locked loop oscillator that can automatically synchronize to a low-speed (32 kHz) crystal. This family does not support EEPROM memory, only mask ROM and UV-eraseable and one-time programmable EPROM. Later families provide only flash ROM and mask ROM options.
MSP430x4xx 
These are similar to the '3xx family, and also include an LCD controller, but are larger and more capable, and come in mask or flash ROM versions.

[edit] Peripherals

The MSP430 peripherals are generally easy to use, with (mostly) consistent addresses between models, and no write-only registers.

[edit] General-purpose I/O ports 0-10

As is standard on microcontrollers, most pins connect to a more specialized peripheral, but if that peripheral is not needed, the pin may be used for general-purpose I/O. The pins are divided into 8-bit groups called "ports", each of which is controlled by a number of 8-bit registers.

The MSP430 family defines 11 I/O ports, P0 through P10, although no chip implements more than 10 of them. P0 is only implemented on the '3xx family. P7 through P10 are only implemented on the largest members of the '4xx family.

PxIN 
Port x input. This is a read-only register, and reflects the current state of the pin.
PxOUT 
Port x output. The values written to this read/write register are driven out the corresponding pins when they are configured to output.
PxDIR 
Port x data direction. Bits written as 1 configure the corresponding pin for output. Bits written as 0 configure the pin for input.
PxSEL 
Port x function select. Bits written as 1 configure the corresponding pin for use by the specialized peripheral. Bits written as 0 configure the pin for general-purpose I/O. Port 0 ('3xx parts only) is not multiplexed with other peripherals and does not have a P0SEL register.
PxREN 
Port x resistor enable ('2xx only). Bits set in this register enable weak pull-up or pull-down resistors on the corresponding I/O pins even when they are configured as inputs. The direction of the pull is set by the bit written to the PxOUT register.
PxIES 
Port x interrupt edge select (ports 0-2 only). Selects the edge which will cause the PxIFG bit to be set. When the input bit changes from matching the PxIES state to not matching it (i.e. whenever a bit in PxIES XOR PxIN changes from clear to set), the corresponding PxIFG bit is set.
PxIFG 
Port x interrupt flag (ports 0-2 only). Set whenever the corresponding pin makes the state change requested by PxIES. Can be cleared only by software. (Can also be set by software.)
PxIE 
Port x interrupt enable (ports 0-2 only). When this bit and the corresponding PxIFG bit are both set, an interrupt is generated.

Note that some pins have special purposes either as inputs or outputs. (For example, timer pins can be configured as capture inputs or PWM outputs.) In this case, the PxDIR bit controls which of the two functions the pin performs even when the PxSEL bit is set. If there is only one special function, then PxDIR is generally ignored.

The PxIN register is still readable if the PxSEL bit is set, but interrupt generation is disabled. If PxSEL is clear, the special function's input is frozen and disconnected from the external pin. Also, configuring a pin for general-purpose output does not disable interrupt generation.

General-purpose I/O register address map
PxIN  PxOUT PxDIR PxSEL PxIES PxIE  PxIFG PxREN
P0 0x10 0x11 0x12 0x13 0x14 0x15
P1 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
P2 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
P3 0x18 0x19 0x1a 0x1b 0x10
P4 0x1c 0x1d 0x1e 0x1f 0x11
P5 0x30 0x31 0x32 0x33 0x12
P6 0x34 0x35 0x36 0x37 0x13
P7 0x38 0x3a 0x3c 0x3e
P8 0x39 0x3b 0x3d 0x3f
P9 0x08 0x0a 0x0c 0x0e
P10 0x09 0x0b 0x0d 0x0f

Ports P7 and P8 may be accessed using 16-bit loads and stores; when used this way, the combination is known as PA. Similarly, P9 and P10 bay be combined into a 16-bit PB.

[edit] Hardware multiplier

Some MSP430 models include a memory-mapped hardware multiplier peripheral which performs various 16×16+32→33-bit multiply-accumulate operations.

Unusually for the MSP430, this peripheral does include an implicit 2-bit write-only register, which makes it effectively impossible to context switch.

The 8 registers used are:

Address Name Function
0x130 MPY Operand1 for unsigned multiply
0x132 MPYS Operand1 for signed multiply
0x134 MAC Operand1 for unsigned multiply-accumulate
0x136 MACS Operand1 for signed multiply-accumulate
0x138 OP2 Second operand for multiply operation
0x13a ResLo Low word of multiply result
0x13c ResHi High word of multiply result
0x13e SumExt Carry out of multiply-accumulate

The first operand is written to one of four 16-bit registers. The address written determines the operation performed. While the value written can be read back from any of the registers, the register number written to cannot be recovered.

If a multiply-accumulate operation is desired, the ResLo and ResHi registers must also be initialized.

Then, each time a write is performed to the OP2 register, a multiply is performed and the result stored or added to the result registers. The SumExt register is a read-only register that contains the carry out of the addition (0 or 1) in case of an unsigned multiply), or the sign extension of the 32-bit sum (0 or -1) in case of a signed multiply. In the case of a signed multiply-accumulate, the SumExt value must be combined with the most significant bit of the prior SumHi contents to determine the true carry out result (-1, 0, or +1).

The result is available after three clock cycles of delay, which is the time required to fetch a following instruction and a following index word. Thus, the delay is typically invisible. An explicit delay is only required if using an indirect addressing mode to fetch the result.

[edit] Development tools

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Texas Instruments provides software development tools that can be downloaded for free. The TI-provided toolchain is a Kickstart edition of the IAR C/C++ compiler, which is limited to 4K of C/C++ code in the compiler and debugger (assembly language programs of any size can be developed and debugged with this free toolchain). TI also provides a version of Eclipse that it calls Code Composer Essentials, for which the Kickstart version can be downloaded for free. The open source community produces a freely available software development toolset (MSPGCC) based on the GNU toolset, although the object code size and speed are not as optimal as the results from a commercial compiler.[citation needed] Also various commercial development toolsets, which include editor, compiler, linker, assembler, debugger and in single cases code wizards, are available. VisSim, a block diagram language for model based development, can generate efficient fixed point C-Code directly from the diagram. By clever use of inline interrupt functions, VisSim generates very efficient control programs that can access I2C, ADC, PWM etc, in a control loop and use less than 1K flash and 128 bytes RAM.

[edit] Development platforms

The MSP430 has generated excitement with the availability of inexpensive development platforms. At a cost of $20 USD, TI has packaged a USB stick programmer, the eZ430-F2013, containing an MSP430F2013 on a detachable prototyping board, and CD with development software. This is helpful for schools, hobbyists and garage inventors. It is also welcomed by engineers in large companies prototyping projects with capital budget problems.

One other interesting thing about the MSP430F2013 and its siblings is that it is the only MSP430 part that is available in a dual in-line package (DIP). Other variants in this family are only available in various surface-mount packages. It is clear that TI has gone to some trouble to support the eZ430 development platform by making the raw chips easily prototypable by hobbyists.

While software development using Linux and other Open Source is possible, support from TI is non-existent, and tool support for new processors is untimely late since they rely on volunteers.

[edit] Debugging interface

In common with other microcontroller vendors, TI has developed a two-wire debugging interface found on all their MSP430 parts that replaces the larger JTAG interface. The eZ430 Development Tool contains a full USB-connected Flash Emulation Tool ("FET") for this new two-wire protocol, named "Spy-Bi-Wire" by TI. Spy-Bi-Wire is currently only available on the MSP430F20xx, MSP430F21x2, and MSP430F22x2 devices.

The advantage of the Spy-Bi-Wire protocol is that it uses only two communication lines, one of which is the dedicated _RESET line. The JTAG interface on the lower pin count MSP430 parts is multiplexed with general purpose I/O lines. This makes it relatively difficult to debug circuits built around the small, low-I/O-budget chips, since the full 4-pin JTAG hardware will conflict with anything else connected to those I/O lines. This problem is alleviated with the Spy-Bi-Wire-capable chips, which are still compatible with the normal JTAG interface for backwards compatibility with the old development tools.

JTAG debugging and flash programming tools based on OpenOCD and widely used in the ARM community are not available for the MSP430. Programming tools specially designed for the MSP430 are marginally less expensive than JTAG interfaces that use OpenOCD. However, should a project discover midstream that more MIPS, more memory, and more I/O peripherals are needed, those tools will not transfer to a processor from another vendor.

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