Three-dimensional integrated circuit
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In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip with two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.
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[edit] 3D ICs vs. 3D Packaging
3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate with off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Essentially, a 3D IC bears the same relation to a 3D package that an SoC bears to a circuit board.
[edit] Manufacturing Technologies
At present (in 2008) there are four ways to build a 3D IC:
Monolithic – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring.
Wafer-on-Wafer – Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon vias” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad.
Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dies may be added to the stacks before dicing.
Die-on-Die – Electronic components are built on multiple dies, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding.
[edit] Benefits
3D ICs offer many significant benefits, including:
Footprint – More functionality fits into a small space. This extends Moore’s Law and enables a new generation of tiny but powerful devices.
Speed – The average wire length becomes much shorter. Because propagation delay is proportional to the square of the wire length, overall performance increases.
Power – Keeping a signal on-chip reduces its power consumption by 10x to 100x[1]. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.
Design – The vertical dimension adds a higher order of connectivity and opens a world of new design possibilities.
Heterogeneous Integration – Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Even more interesting, components with completely incompatible manufacturing could be combined in a single device[2].
Circuit Security - The stacked structure hinders attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.[3]
[edit] Challenges
Because this technology is new it carries new challenges, including:
Yield – Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects must be avoided or repaired[4].
Heat – Thermal buildup within the stack must be prevented or dissipated.
Design Complexity – Taking full advantage of 3D requires intricate and elegant multi-level designs. Chip designers will need new CAD tools to address the 3D paradigm.[5]
[edit] External Links
[edit] Early Products
- 2001, Monolithic write-once memory: “Matrix preps 64-Mbyte write-once memory” EE Times
- 2004, Wafer-to-wafer RAM: “MagnaChip, Tezzaron form partnership for 3D chips” EE Times
- 2007, Die-to-wafer focal plane array: “Ziptronix, Raytheon Prove 3-D Integration of 0.5 µm CMOS Device” Semiconductor International
[edit] Organizations
[edit] Selected Press References
- 2003, EE Design: “Three-dimensional SoCs perform for future”
- 2004, EDN: “3D Interconnect Technology Coming to Light”
- 2005, Semiconductor International: “Three-Dimensional ICs Solve the Interconnect Paradox”
- 2006, Solid State Technology: “Mapping progress in 3D IC integration”
- 2007, Nikkei Electronics Asia: “Vertical Stacking to Redefine Chip Design”
[edit] References
- ^ William J. Dally, “Future Directions for On-Chip Interconnection Networks” page 17, http://www.ece.ucdavis.edu/~ocin06/talks/dally.pdf Computer Systems Laboratory Stanford University, 2006
- ^ James J-Q Lu, Ken Rose, & Susan Vitkavage “3D Integration: Why, What, Who, When?” http://www.future-fab.com/documents.asp?d_ID=4396 Future Fab Intl. Volume 23, 2007
- ^ "3D-ICs and Integrated Circuit Security" http://www.tezzaron.com/about/papers/3D-ICs_and_Integrated_Circuit_Security.pdf Tezzaron Semiconductor, 2008
- ^ Robert Patti, "Impact of Wafer-Level 3D Stacking on the Yield of ICs" http://www.future-fab.com/documents.asp?d_ID=4415 Future Fab Intl. Volume 23, 2007
- ^ "EDA's big three unready for 3D chip packaging" http://www.eetasia.com/ART_8800485666_480300_NT_fcb98510.HTM EE Times Asia October 25, 2007
