Talk:Threshold voltage

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Improved/Advanced

For above article; note that not the gate voltage but "gate-to-source" voltage is the determinant one.

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For an enhancement type NMOS device, if the gate-to-source voltage is higher than the threshold voltage; there exists enough enough electrons to connect the n+ doped source and drain, and the transistor begins to conduct through from drain to source.

Note that the magnitude of this current is depends on the Vgs (gate - to -drain) voltage. As much the Vgs>Vt higher th current flows.

The simple equation is given below:(For ENHANCEMENT type NMOS device)

Ids = (1/2)Kn(Vgs - Vt)^2 if Vgs-Vt Vds and this situation is called SATURATION Mode; Ids = Kn(Vgs -Vt - Vds/2)Vds if Vgs-Vt Vds and this situation is called LINEAR Mode;

Also Threshold is dependent of the bulk-to-source voltage (Vbs). If Vbs=0 it is simply the Vt=Vto defined by the process. But if Vbs is started to increase so the Vt, and Vt!=Vto anymore. There exist also an equation between Vt&Vbs. (Too advanced to give here, but if you like look any Microelectronic Electronics Book)

For a PMOS enhancement type transistor; you need to construct an depletion layer with holes not with the electrons; so you should apply negative voltage to attract holes; which results in a negative Vt. In fact instead of that the convention for PMOS is simply defining Vsg (source to gate voltage) rather than using Vgs. Pls note that he above equations differ for pmos case (look Microelectronic Circuit Design, Jaeger)( Vt<0; Vgs<Vt<0 to be on)

There exist also depletion type MOSFETS where the depletion layer is implemented by doping, i.e. with no voltage applied you have an depletion layer and the device is conducting with zero bias. In these devices the threshold voltage may be defined as the Vgs you applied for closing the depletion layer for sake of simplycity. (if you are lower than that voltage than the device will be closed, so to turn it on Vgs should reside in Vgs>Vt but Vt<0;) (note the difference between PMOS enhancement) That is, for the NMOS case there is an depletion layer already formed with n doped poly; and for the PMOS case there exists a depletion layer formed with p doped poly.

The threshold voltage varies depending of the device type; and the process. Summary is below.

For enhancement type to be on:

                     NMOS          Vgs>Vt>0;
                     PMOS          0>Vt>Vgs;

For depletion Type to be on:

                     NMOS          0>Vt; Vgs>Vt;
                     PMOS          0<Vt; Vgs<Vt;