Subthreshold leakage

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Subthreshold leakage of an NMOS
Subthreshold leakage of an NMOS

Subthreshold leakage or subthreshold conduction or subthreshold drain current is the current that flows between the source and drain of a MOSFET when the transistor is in the subthreshold region, that is, for gate-to-source voltages below the threshold voltage. The subthreshold region is often referred to as the weak inversion region. The terminology for various degrees of inversion is described in Tsividis.[1]

In digital circuits, subthreshold conduction is generally viewed as a parasitic leakage in a state that would ideally have no current. In micropower analog circuits, on the other hand, weak inversion is an efficient operating region, and subthreshold is a useful transistor mode around which circuit functions are designed.

In the past, the subthreshold conduction of transistors has been very small, but as transistors have been scaled down, leakage from all sources has increased. For a technology generation with threshold voltage of 0.2 V, leakage can exceed 50% of total power consumption.[2] Subthreshold conduction is only one component of leakage: other leakage components that can be roughly equal in size depending on the device design are gate-oxide leakage and junction leakage.[3]

The reason for a growing importance of subthreshold conduction is that the supply voltage has continually scaled down, both to reduce the dynamic power consumption of integrated circuits (the power that is consumed when the transistor is switching from an on-state to an off-state, which depends on the square of the supply voltage), and to keep electric fields inside small devices low, to maintain device reliability. There are also other sources of leakage power such as gate tunneling and junction tunneling. Understanding sources of leakage and solutions to tackle the impact of leakage will be a requirement for most circuit and system designers. [4]

The amount of subthreshold conduction is set by the threshold voltage, which sits between ground and the supply voltage, and so has to be reduced along with the supply voltage. That reduction means less gate voltage swing below threshold to turn the device off, and as subthreshold conduction varies exponentially with gate voltage (see MOSFET: Cut-off Mode ), it becomes more and more significant as MOSFETs shrink in size.[5]

[edit] References

  1. ^ Yannis Tsividis (1999). Operation and Modeling of the MOS Transistor, Second Edition, New York: McGraw-Hill, p. 99. ISBN 0-07-065523-5. 
  2. ^ Kaushik Roy, Kiat Seng Yeo (2004). Low Voltage, Low Power VLSI Subsystems. McGraw-Hill Professional, Fig. 2.1, p. 44. ISBN 007143786X. 
  3. ^ Bashir M. Al-Hashimi (Editor) (2006). System on a Chip: Next Generation Electronics. Institution of Engineering and Technology, p. 429. ISBN 0863415520. 
  4. ^ Siva G. Narendra and Anantha Chandrakasan (Editors) (2006). Leakage in Nanometer CMOS Technologies. Springer Publications, p. 307. ISBN 0387257373. 
  5. ^ Dimitrios Soudris, Christian Piguet, and Costas Goutis (Editors) (2002). Designing CMOS Circuits for Low Power. Springer. ISBN 1402072341. 
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