Speed-demons
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Speed demon is a term which sometimes has been used to denote a CPU design which favors high clock speed over high instructions per clock (IPC), particulary regarding modern "CISC" processors for personal computers. Speed demon designs typically employ longer pipelines, sometimes also different implementations of low-level logic, or optimisations of the manufacturing process, than most "brainiac" designs do.
Brainiac designs tend to optimize performance by having each execution step do as much as possible (using many logic levels) in order to achieve high performance at moderate clock frequencies, and also permit program branches without much penalty. Modern speed demon designs (such as Pentium 4) have instead tried to combine simpler (and thus individually faster) pipeline steps with very elaborate branch prediction, as well as combining (partly) unconventional low-level logic implementations (differential signaling etc) with a very refined manufacturing process in order to achieve high frequencies without excessive heat production.
Examples of speed demon CPUs include the Pentium 4, especially the Prescott, which was designed with a 31-stage pipeline, compared to 20 stages for the Northwood, 12 stages for the Athlon 64, and 10 stages for the Athlon XP.
As of 2008, it appears that[who?], at least in the popular x86 family, the CPU industry is moving away from the speed demon design. While the Pentium 4 was originally forecast to run at up to 10 GHz, and in reality topped out at 3.8 GHz, both Intel's and AMD's current top performing CPUs are actually clocked well below 3.8 GHz.
In another, somewhat wider, perspective than x86 processors or personal computers, one could say that large parts of the CPU industry first started to move away from "brainiac" CPUs towards speed-demon CPUs already in the mid 1970s, with the movement towards RISC (although there had been several even earlier cases of RISC-like designs).
