Shallow trench isolation
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Shallow trench isolation (STI), also known as 'Box Isolation Technique', is an integrated circuit feature which prevents electrical current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.[1]
STI is created early during the semiconductor device fabrication process, before transistors are formed. The key steps of the STI process involve etching a pattern of trenches in the silicon, depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization.[1]
Certain semiconductor fabrication technologies also include deep trench isolation, a related feature often found in analog integrated circuits.
[edit] References
- ^ Quirk, Michael & Julian Serda (2001). Semiconductor Manufacturing Technology: Instructor's Manual, p. 25.
[edit] External links
- Clarycon: Shallow trench isolation
- N and K Technologies: Shallow trench isolation
- Dow Corning: Spin on Dielectrics - Spin-on Shallow Trench Isolation
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