Talk:Serial Peripheral Interface Bus

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[edit] Early comments

"A serial peripheral bus is the most flexible choice [...]"

"[...] making it an excellent choice for some data transmission systems."

"SPI looks at first like a non-standard. However, [...]"

"The interface is also easy to implement for bench test equipment [...]"


This article is well written, but does anyone else get the feeling that this article was written by the SPI Promotional Society?

--Dan McCarty 14:52, 21 June 2006 (UTC)

I have to disagree on both counts! I don't think the article is very well written, (though I've seen worse). To me it reads like it was written by an engineering student who's just learnt about SPI, and therefore doesn't have much context to hang it on. It also suffers from having the waffly marketing-type crud you highlighted, presumably for padding and to cover gaps.

I'll try to edit it over the next few days. Please let me know what you think.

--Ianlewis 12:30, 3 August 2006 (UTC)

Should we mention these similar-sounding interface buses?

Serial Digital Interface DVB-SPI SCSI Parallel Interface

--65.70.89.241 20:16, 6 September 2006 (UTC)

I would have to say no. Mainly because they are unrelated. Certainly not the SCSI or DVB-SPI ones (they are both parallel). And SDI - a very dissimilar interface. SPI is a basic interface, and I think only basic/lowlevel interfaces should be mentioned w/ it.

--User:RonB 13:56, 6 September 2006 (CST)

Yes, physically they are very different. But all of them have the same acronym -- SPI. So people that are looking for information on something spelled "SPI" might appreciate a hint as to where to find what they are looking for. So I think this article should mention the other things called "SPI" -- similar to the way the top of the optoisolator page helps people find what they were really looking for, when they were really looking for a opto-isolator. --75.37.227.177 05:08, 26 July 2007 (UTC)

[edit] accross boards or single board

Is SPI used as an interconnect across boards, or is it an onboard bus only? —Preceding unsigned comment added by 63.231.83.177 (talk • contribs) there is no reason it can't be used accross boards, the standard doesn't define any standard connectors though and as the article says its a very loose standard. As with any bus of this nature achiveable distances will depend heavilly on clock speed and characteristics of the interconnecting lines. Plugwash 23:36, 7 October 2006 (UTC)

[edit] Parallel port voltage

The parallel port voltage level on the most recent PCs is less than 5V. This can make it difficult to use it for direct SPI control, so some sort of interface IC is usually needed. DFH 12:03, 3 November 2006 (UTC)

[edit] Upper Canada Technologies

Upper Canada Technologies was the company that supplied the "IOport" driver to enable WinNT machines to directly control the parallel port. Their web address was http://www.uct.on.ca/ but this is no longer a valid URL. DFH 12:11, 3 November 2006 (UTC)

[edit] Need more details

The page needs more details IMO; sorry I have time to gripe about it now, but not enough to fix it much (I'm researching on whether disabling the frame select/chip select is mandatory between frames when SCPH=0, and my boss is checking every no and then...). Even the external links don't have much detail. 202.33.138.40 05:13, 29 November 2006 (UTC)

[edit] Daisy chain connection of several SPI slaves

A diagram depicting this would be a useful addition to the article. DFH 19:08, 21 December 2006 (UTC)

I'll put it on my list to do. Can you name any specific devices that do daisy chaining? Cburnett 19:26, 21 December 2006 (UTC)
Freescale (Intelligent High Current Self-Protected Hi-Side Switch) MC33982[1] and MC33984[2] both support daisy chain. DFH 20:54, 22 December 2006 (UTC)
Done. Cburnett 20:58, 21 December 2006 (UTC)
Thanks, but I noticed there is a line missing from slave 3 back to the master. DFH 20:48, 22 December 2006 (UTC)
Fixed. Cburnett 00:16, 26 December 2006 (UTC)
Thank you. 57.66.65.38 13:35, 4 January 2007 (UTC)

Suggestion for most of the pictures showing master and one or more slaves: use a different color for the chipselect signal(s), so they stand out more. Or different thickness, hatching etc ... colorblind people use Wikipedia too! 69.226.247.176 19:19, 14 August 2007 (UTC)

[edit] QSPI

We don't need a separate Wikipedia article about Queued Serial Periperal Interface (QSPI). An additional section in this article would suffice. Any volunteers? I am therefore removing the QSPI redlink from the See also section. DFH 19:37, 21 December 2006 (UTC)

I created the respective redirects: QSPI, Queued Serial Peripheral Interface Bus, Serial Peripheral Interface. Cburnett 20:11, 21 December 2006 (UTC)
Do you have any documentation on it? I can't seem to find any good docs in my quick google search. Cburnett 03:21, 22 December 2006 (UTC)
I too did a quick Google search yesterday, yet didn't stumble upon a proper spec. There are probably some Motorola or Freescale products which embody it. I will search again soon. DFH 20:46, 22 December 2006 (UTC)
U.S. Patent 4,816,996 , U.S. Patent 4,958,277 , U.S. Patent 5,805,922  are examples of QSPI. DFH 22:18, 22 December 2006 (UTC)
This section now cites a useful reference. DFH 20:23, 5 January 2007 (UTC)

This wrongly presented QSPI as if it was a new kind of SPI; it's not. It's just one of many controller interfacew. I just updated this, along with a lot of other stuff that was excessively specific to the use of SPI on certain Freescale products ... whence all these eight bit restrictions, gaagh! At this point I have no clue what sort of "expansion" would be appropriate there.

[edit] Why is bus capitalized in the article's title ?

Bus is not a proper noun, nor is it part of the acronym. Should the title be changed to Serial Peripheral Interface bus (by means of a page move)? DFH 21:16, 22 December 2006 (UTC)

I'd say drop the "bus" altogether. If not that, then lowercase "bus". Cburnett 21:26, 22 December 2006 (UTC)
It seems the article began (or was duplicated) as Serial Peripheral Interface, which is now a redirect to here, but has some edit history. These circumstances make a move back more difficult. It may be simpler just to make "bus" lowercase. DFH 22:01, 22 December 2006 (UTC)

[edit] Clock phase and polarity

I am about to replace the particular example "For example, the LPC2104/2105/2106 (a ARM7TDMI 60 MHz microcontroller)" by a reference to the SPI Block Guide. DFH 16:35, 4 January 2007 (UTC)

Glad to see a more generic reference! Cburnett 20:14, 4 January 2007 (UTC)

[edit] Missing Bar over SS

The bars over SS are missing.(There should be bars over SS to indicate the Active Low nature) —The preceding unsigned comment was added by 203.91.193.50 (talk) 10:03, 6 March 2007 (UTC).

I agree, maybe these should be here. Especially since the broad nature of the article uses the notion that SS is always asserted when the line is pulled low (and idle high). Now granted, EVERY chip that I have used makes this the state of operation, but is this a given for all parts or is this just a convention that most choose to follow? And generally, this is defined by the slave parts, since most parts that implement master mode don't allow use of the SS line as a assertion out line.--Ronb 16:32, 7 April 2007 (UTC)
Done. Cburnett 16:41, 7 April 2007 (UTC)
My two cents: use the 'nCS' convention (or if you must, 'nSS') rather than trying for fancy typography.

I just updated the article to point out that chipselects are not always active low. -- 69.226.212.132 06:09, 2 June 2007 (UTC)

[edit] MicroWire

IMO there's no point in having a separate page on MicroWire. Maybe someone with an account can merge that one into this page. Ideally there should be a bit more info there, too. --69.226.212.132 06:12, 2 June 2007 (UTC)

[edit] Shift register picture desirable

Someone with a bit of time to create art might consider the classic picture showing how the master and slave side shift registers hook up to each other. SPI controller documentation for most SOC chips will have such a picture. When updating the description of data transfer, I added verbiage to say what happens ... but that's very amenable to a picture (pick some oddball word size, maybe 11 bits). That level of presentation -- words, not bits -- has been mostly missing; which is too bad since it's the level that most developers think at. --69.226.212.132 06:20, 2 June 2007 (UTC)

I have added an image. Comments and suggestions? Cburnett 01:55, 25 June 2007 (UTC)
Artwork ... thanks! My first reaction was that showing the memory is a bit confusing; it's just sitting there. I'd suggest just focussing on the shifty bits; getting beyond that starts to get into structures that won't exist in all controllers (like tx/rx buffer registers, possibly backed by FIFOs or with DMA, etc). A picture I happened to have readily at hand is Fig 17-2 in Atmel's ATmega168 spec ... no memory drawn, but it does show the master with clock generator and managing chipselect. On closer examination, the bit numbering is also a bit confusing. Normally bit 0 is the LSB and would be shown on the right ... here it's shown on the left! But in deference to those heretical systsems where bit 0 is the MSB (and thus is shown on the left), it might be better to just label "MSB" and "LSB". I hope you prefer "copious feedback" to "grunt, yeah". ;) 69.226.213.6 15:54, 28 June 2007 (UTC)
I was thinking and planning a short series of images: a copy from memory to the buffer; then the transfer; then storing back to memory. I was waiting for feedback before investing that much work. Hindsight says I should have mentioned this above. :) I always welcome constructive feedback! Cburnett 16:32, 28 June 2007 (UTC)

[edit] so where can one find it?

It would be useful if somebody could explain where generally the SPI devices are to be found. 83.208.14.127 00:56, 25 June 2007 (UTC)

Guess I'm not sure what you mean. You can find it on many, many microcontrollers (PIC, Atmel, Philips, etc.) and many, many devices (Maxim for one). Cburnett 01:35, 25 June 2007 (UTC)
I'm not sure either. Most distributors have on-line catalogs nowadays, and you can probably just enter SPI as a search key. I've done that with DigiKey(.com) with success. Chip vendors don't tend to sort by interconnect though; if you want a Zigbee chip, you'd just have to *know* that they almost universally talk SPI. (Except for modules that embed a SPI chip and a microcontroller, offering a "high level" interface with a UART or something to the micro.) 69.226.213.6 15:31, 28 June 2007 (UTC)

I'm looking for a microcontroller with at least 3 SPI ports, preferably more. (I have a pile of SPI peripherals that unfortunately can't share the same bus). So far the only microcontroller I've found with 3 SPI ports is the "Intel PXA270" XScale processor.

(I suppose I should also consider simulating SPI ports with "bit-banging" GPIO pins, and also programming a FPGA or FPSLIC to handle SPI).

Are there other microcontrollers that I should look at? --75.37.227.177 05:08, 26 July 2007 (UTC)

Yes; I'm no PXA fan, myself. The key is: don't limit yourself to SPI-specific controllers. ISTR that pxa270 doesn't have dedicated SPI; it has a multipurpose SSP controller which can be used in SPI mode (among other modes including I2S). Lots of controllers have similar multipurpose serial ports ... OMAP1 has McBSP, which can be used in SPI mode, so an OMAP5912 supports a whole bunch of SPI: 3 McBSP ports, one MicroWire, one SPI ... two MMC slots with SPI support, and ISTR a few other controllers too. Atmel AT91rm9200 has one SPI and three SSC; AT91sam9261 has two spi and three SSC, as does the AVR32 AT32AP7000. And yes, bitbanging SPI is really easy, depending on the data rates you need and how much CPU bandwidth you have free. 69.226.247.176 19:15, 14 August 2007 (UTC)
Another option may be to use some basic logic chips (or a PAL) to gate the SPI outputs so that only one chip at a time sees SPI activity even though the controller has only one SPI interface. Plugwash 00:18, 15 August 2007 (UTC)

[edit] JTAG

It seems like a bit of a stretch to call JTAG an "application stack" for SPI. Yes, JTAG and SPI are both serial shift registers. But that's about all they have in common. It's flat wrong to imply that TMS is SSn with a 'different signal name'. The way TMS is used in JTAG is not generally equivalent to or compatible with the way SSn is used in SPI. You couldn't, for example, hook up a generic microcontroller SPI master directly to a JTAG port and expect it to work--at least not without a lot of manual bit-banging to get the required behavior on TMS (toggle around for a few cycles to begin shifting; put TMS high on last data bit, etc). 192.94.94.105 17:15, 28 June 2007 (UTC)

There are other SPI protocols, including MMC/SD in SPI mode, that have "strange" rules about chipselect signaling. (MMC/SD has cases where it requires clocks and data to go out when chipselect is inactive.) And they don't shy away from calling themselves "SPI". Generic microcontrollers tend to cheap out on SPI hardware, with restrictions like only handling 8 bit words unless they clock bits out "by hand", and not being able to support all modes; that makes it difficult to use them to master some SPI devices. But that doesn't affect the truth that JTAG is layered over the four signal wires of SPI ... which is quite a lot to have in common, given that's about all that SPI covers! And in any case, the value (and complexity) of JTAG is in that stack, not the lowlevel signaling. Vendor commands, BSDL, etc. 69.226.213.6

[edit] Picture of Bus interface problem

There seems to be a problem with the first picture for the SPI interface. The MOSI of the Master should go to the MISO of the slave and the MOSI of the slave to the MISO of the master. —Preceding unsigned comment added by Mihaigalos (talk • contribs) 22:02, 6 October 2007 (UTC)

MOSI means "master out, slave in". So the MOSI pins get connected together and MISO pins get connected together. Thus, you don't have to rewire if you switch the master around. Cburnett 04:32, 7 October 2007 (UTC)