Satisfiability Modulo Theories

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Satisfiability Modulo Theories (SMT) problem is a decision problem for logical formulas with respect to combinations of background theories expressed in classical first-order logic with equality. Examples of theories typically used in computer science are the theory of real numbers, the theory of integers, and the theories of various data structures such as lists, arrays, bit vectors and so on.

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[edit] Basic terminology

Formally speaking, an SMT instance is a formula in first-order logic, where some function and predicate symbols have additional interpretations, and SMT is the problem of determining whether such a formula is satisfiable. In other words, imagine an instance of the Boolean satisfiability problem (SAT) in which some of the binary variables are replaced by predicates over a suitable set of non-binary variables. A predicate is basically a binary-valued function of non-binary variables. Example predicates include linear inequalities (e.g., 3x+ 2y - z \geq 4) or equalities involving so-called uninterpreted terms and function symbols (e.g., f(f(u,v),v) = f(u,v) where f is some unspecified function of two unspecified arguments.) These predicates are classified according to the theory they belong to. For instance, linear inequalities over real variables are evaluated using the rules of the theory of linear real arithmetic, whereas predicates involving uninterpreted terms and function symbols are evaluated using the rules of the theory of uninterpreted functions with equality (sometimes referred to as the empty theory [1]). Other theories include the theories of arrays and list structures (useful for modeling and verifying software programs), and the theory of bit vectors (useful in modeling and verifying hardware designs). Subtheories are also possible: for example, difference logic is a sub-theory of linear arithmetic in which each inequality is restricted to have the form x - y \leq c for variables x and y and constant c.

Most SMT solvers support only quantifier free fragments of their logics.

[edit] Expressive power of SMT

An SMT instance is a generalization of a Boolean SAT instance in which various sets of variables are replaced by predicates from a variety of underlying theories. Obviously, SMT formulas provide a much richer modeling language than is possible with Boolean SAT formulas. For example, an SMT formula allows us to model the datapath operations of a microprocessor at the word rather than the bit level.

[edit] SMT solvers

Early attempts for solving SMT instances involved translating them to Boolean SAT instances (e.g., a 32-bit integer variable would be encoded by 32 bit variables with appropriate weights and word-level operations such as 'plus' would be replaced by lower-level logic operations on the bits) and passing this formula to a Boolean SAT solver. This approach has its merits: by pre-processing the SMT formula into an equivalent Boolean SAT formula we can use existing Boolean SAT solvers "as-is" and leverage their performance and capacity improvements over time. On the other hand, the loss of the high-level semantics of the underlying theories means that the Boolean SAT solver has to work a lot harder than necessary to discover "obvious" facts (such as x + y = y + x for integer addition.) This observation led to the development of a number of SMT solvers that tightly integrate the Boolean reasoning of a DPLL-style search with theory-specific solvers that handle conjunctions (ANDs) of predicates from a given theory.

Dubbed DPLL(T), this architecture gives the responsibility of Boolean reasoning to the DPLL-based SAT solver which, in turn, interacts with a solver for theory T through a well-defined interface. The theory solver need only worry about checking the feasibility of conjunctions of theory predicates passed on to it from the SAT solver as it explores the Boolean search space of the formula. For this integration to work well, however, the theory solver must be able to participate in propagation and conflict analysis, i.e., it must be able to infer new facts from already established facts, as well as to supply succinct explanations of infeasibility when theory conflicts arise. In other words, the theory solver must be incremental and backtrackable.

CVC (for Cooperating Validity Checker) is an automatic theorem prover for the Satisfiability Modulo Theories problem. It was developed originally by the Stanford Verification Group as a successor to the Stanford Validity Checker, but is now maintained primarily by researchers at New York University and the University of Iowa. Its latest release is version 3.0 or CVC3. Previous releases were called CVC Lite (v2.0) and CVC (v1.0).

[edit] SMT for undecidable theories

Most of the common SMT approaches support decidable theories. However, many real-world systems can only be modelled by means of non-linear arithmetic over the real numbers involving transcendental functions, e.g. an aircraft and its behavior. This fact motivates an extension of the SMT problem to non-linear theories, e.g. determine whether (\sin(x)^3 = \cos(\log(y)\cdot x) \vee b \vee -x^2 \geq 2.3y) \wedge (\neg b \vee y < -34.4 \vee \exp(x) > y/x) where b \in {\mathbb B}, x,y \in {\mathbb R} is satisfiable. Then, such problems become undecidable in general. (It is important to note, however, that the theory of Real Closed Fields, and thus the full first order theory of the Real Numbers, are decidable. This is due to Tarski.)

Examples of SMT solvers addressing Boolean combinations of theory atoms from undecidable arithmetic theories over the reals are ABsolver (Bauer, Pister & Tautschnig 2007), which employs a classical DPLL(T) architecture with a non-linear optimization packet as (necessarily incomplete) subordinate theory solver, and HySAT-2, building on a unification of DPLL SAT-solving and interval constraint propagation called the iSAT algorithm (Fränzle et al. 2007).

[edit] External links

[edit] SMT Solvers

[edit] References

  1. Bauer, A.; Pister, M. & Tautschnig, M. (2007), “Tool-support for the analysis of hybrid systems and models”, Proceedings of the 2007 Conference on Design, Automation and Test in Europe (DATE'07), IEEE Computer Society, DOI 10.1109/DATE.2007.364411 
  2. R. E. Bryant, S. M. German, and M. N. Velev, "Microprocessor Verification Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted Functions," in Analytic Tableaux and Related Methods, pp. 1-13, 1999.
  3. M. Davis and H. Putnam, A Computing Procedure for Quantification Theory , Journal of the Association for Computing Machinery, vol. 7, no., pp. 201-215, 1960.
  4. M. Davis, G. Logemann, and D. Loveland, A Machine Program for Theorem-Proving , Communications of the ACM, vol. 5, no. 7, pp. 394-397, 1962.
  5. Fränzle, M.; Herde, C.; Ratschan, S.; Schubert, T. & Teige, T. (2007), “Efficient Solving of Large Non-linear Arithmetic Constraint Systems with Complex Boolean Structure”, JSAT Special Issue on SAT/CP Integration, vol. 1, pp. 209-236, <http://jsat.ewi.tudelft.nl/content/volume1/JSAT1_11_Fraenzle.pdf> 
  1. D. Kroening and O. Strichman, Decision Procedures - an algorithmic point of view (2008), Springer (Theoretical Computer Science series) ISBN 978-3540741046.
  2. G.-J. Nam, K. A. Sakallah, and R. Rutenbar, A New FPGA Detailed Routing Approach via Search-Based Boolean Satisfiability , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 6, pp. 674-684, 2002.
  3. C. Tinelli, "A DPLL-based Calculus for Ground Satisfiability Modulo Theories," in Europ. Conf. on Logic in AI (JELIA), pp., 2002.

This article is adapted from a column in the ACM SIGDA e-newsletter by Prof. Karem Sakallah
 Original text is available here.

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