Reduced Media Independent Interface

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Reduced Media Independent Interface (RMII) is a standard that addresses the connection of Ethernet physical layer transceivers (PHY) to Ethernet switches. It reduces the number of signals/pins required for connecting to the PHY from 16 (for an MII-compliant interface) to between 6 and 10. RMII is capable of supporting 10 and 100 Mbit/s; gigabit interfaces need a wider interface.

An Ethernet interface normally consists of 4 major parts: The MAC (Media Access Controller), the PHY (PHYsical Interface or transceiver), the magnetics, and the connector. Connectors with integrated magnetics are available. The MAC handles the high level portions of the Ethernet protocol (framing, error detection, when to transmit, etc) and the PHY handles the low level logic (4B/5B encoding/decoding, SERDES (serialization/deserialization), and NRZI encoding/decoding) and analog portions. RMII is one of the possible interfaces between the MAC and PHY; others include MII and SNI, with additional wider interfaces (including XAUI, GBIC, SFP, SFF, XFP, and XFI) for gigabit and faster Ethernet links. One or more MAC interfaces may be on the same chip and in some cases the chip may have many other functions. One or more PHY interfaces may be on the same chip, particularly in Ethernet switches. Some MAC and PHY ICs support both MII and RMII. Usually, the MAC and PHY are on the same board for 10/100 Ethernet though for gigabit and higher pluggable PHY modules may be used to allow the use of different media including twisted pair and optical fiber. Older coaxial Ethernet interfaces sometimes used an AUI interface between the MAC and transceiver which was often an external box (thicknet required an external transceiver).

By comparison, the MII interface requires two additional data lines in each direction, RX_DV and CRS are separate rather than multiplexed, a separate TX_CLK and RX_CLK are used instead of a shared reference clock, and a collision signal is added for a total of 7 additional lines. The added pin count is more of a burden on microcontrollers with built in MAC, FPGA's, multitport switches or repeaters, and PC motherboard chipsets than it is for a separate single port Ethernet MAC which partially explains why the older MII standard was more wasteful of pins.

[edit] Signals

TXD0 Transmit data bit 0 (MAC to PHY) (transmitted first)
TXD1 Transmit data bit 1 (MAC to PHY)
TX_EN When high, clock data on TXD0 and TXD1 to the transmitter (MAC to PHY)
RXD0 Receive data bit 0 (PHY to MAC) (received first)
RXD1 Reveive data bit 1 (PHY to MAC)
CRS_DV, Carrier Sense (CRS)/RX_Data Valid(RX_DV) multiplexed on alternate clock cycles. In 10 Mbit/s mode, it alternates every 10 clock cycles. (PHY to MAC)
RX_ER Receive Error (optional on switches) (PHY to MAC)
REF_CLK Continuous 50 MHz Reference Clock (may be shared among interfaces). Reference clock may be an input on both devices or may be driven from MAC to PHY.
MDIO Management data I/O line (IIC/SMBus/TWI compatible) (bidirectional, open drain)
MDC Management data clock line (bidirectional but MAC to PHY in practice (though perhaps the PHY can pull down MDC to slow transfer), open drain). MDC and MDIO can in some cases be shared among multiple PHYs and with other devices.

On multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port.

RMII requires a 50 MHz clock where MII requires a 25 MHz clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (10 Mbit/s only). Data is not double pumped; i.e. data is sampled only on the rising edge.

The Atmel AT91SAM7XC128/256/512 microcontrollers define an additional signal in RMII mode called EF100 [1] which is supposed to force 100 Mbit/s operation but fails to specify details of its use. It seems unnecessary as this can be configured over the management interface and it allows forcing of only one of 4 force-able modes (10/100 Mbit/s and full/half duplex).

In 10 Mbit/s mode, TXD0/TXD1/RXD0/RXD1 are sampled on every tenth clock cycle. The standard does a poor job of explaining the timing of signals in 10 Mbit/s mode. Apparently data on signal lines is supposed to remain valid for 10 clock cycles so it can be sampled on any clock edge during that interval. TX_EN probably remains asserted for the duration of the packet. It appears that 10 Mbit/s mode can be implemented by inserting a divide by 10 prescaler with pulse gate or separate clock enable line. It does not appear that the prescaler has to be reset to synchronize it with any particular event; instead the two prescalers (MAC and PHY) operate asynchronously with respect to each other.

There is no signal which defines whether the interface is in 10 or 100 Mbit/s mode but obviously both the MAC and the PHY need to agree. This is presumably handled by the MDIO/MDC interface though things might get interesting if the PHY and switch renegotiate the link speed at an unexpected time (perhaps after a cable was disconnected and reconnected). Future versions of the RMII standard might specify a way to transmit data over TXD0/TXD1/RXD0/RXD1 pins while TX_EN and CRS_DV are de-asserted.

The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC.

TTL signal levels are used for 5V or 3.3V logic. Input high threshold is 2.0V and low is 0.8V. The specification specifies that inputs should be 5V tolerant, however, some popular chips with RMII interfaces are not 5V tolerant. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of 5V tolerance is probably very common, and chips that actually drive 5V are probably even rarer. 5V tolerance is probably found primarily on older MII only devices. On the other hand, newer devices may support 2.5 and 1.8V logic. National doesn't make 5V tolerant RMII PHYs. National DP83848: no 5V. SMSC LAN8187: 1.8V to 3.3V, not 5V tolerant. Intel LXT9781/LXT9761 8/6 port PHY: 5v tolerant. Atmel AT91SAM7XC256 microcontroller: 5V tolerant, AMD 79C875 4 port PHY: 5V tolerant, FPGAs sufficient to implement MAC are usually not 5V tolerant.

The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive (and thus slew rates) need to be as slow as possible (rise times from 1 to 5ns) in order to permit this. Drivers should be able to drive 25pf of capacitance which allows for PCB traces up to 12 inches. At least the standard says the signals need not be treated as transmission lines; however, at 1ns edge rates a trace longer than about 1.1 inches (1ns/(1.8ns/ft)*(12 ft/in)*(1/6)), transmission line effects could be a significant problem; at 5ns, traces can be five times longer. The IEEE version of the related MII standard specifies 68 Ω trace impedance [2] and National AN-1469 recommends running 50 Ω traces with 33 Ω (adds to driver output impedance) series termination resistors for either MII or RMII mode to reduce reflections and suggests that traces be kept under 6" long and matched within 2" on length to minimize skew.

Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode [3].