PSE-36
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In computing, PSE-36 refers to a feature of x86 processors that extends the physical memory addressing capabilities from 32 bits to 36 bits. This mechanism is a simpler alternative to the Physical Address Extension (PAE) method. It uses the Page Size Extension (PSE) mode and a modified page directory table to map 4 megabyte (MB) pages into a 64 gigabyte (GB) physical address space.[1] PSE-36 was introduced into the x86 with the Pentium III architecture. [2]
[edit] Operation
Enabling PSE alone (by setting bit 4, PSE, of the system register CR4) allows to use large 4 MB pages along with normal 4 KB pages.
If newer PSE-36 capability is available on the CPU, as checked using the CPUID instruction, then 4 more bits, in addition to the 10 bits used in PSE, are used inside a page directory entry pointing to a large page. This allows a large page to be located in 36 bit address space.
PAE also allows 36-bit addressing. PSE-36 has the advantages that the hierarchy of page tables is not changed, and that page entries keep their old 32-bit format and are not extended to 64 bits. The obvious disadvantage of PSE-36 is that only large pages can be located in 64 GB of physical memory, and small pages can still be located only in the first 4 GB of physical memory.
Page Directory Entry (PDE) structures in normal mode, PSE mode, and PSE-36 mode are as follows:
| + | 31-22 | 21-18 | 17-12 | 11-9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-PSE | base | avail | 0 | PS | 0 | A | PCD | PWT | U | W | P | |||||||||||||||||||||
| PSE | frame | avail | 0 | PS | D | A | PCD | PWT | U | W | P | |||||||||||||||||||||
| PSE-36 | frame | avail | 0 | PS | D | A | PCD | PWT | U | W | P | |||||||||||||||||||||
[edit] See also
[edit] References
- ^ 1 GB = 1024 MB ; 1 MB = 1024 KB ; 1 KB = 1024 B
- ^ (August, 2007) Intel 64 and IA-32 Architectures Software Developer's Manuals Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Intel Corporation, pp. 3-40 to 3-41. "The PSE-36 mechanism was introduced into the IA-32 architecture with the Pentium III processors."
