Prefetch buffer
From Wikipedia, the free encyclopedia
 |
This article needs additional citations for verification. Please help improve this article by adding reliable references. Unsourced material may be challenged and removed. (May 2007) |
The prefetch buffer is a memory cache located on modern RAM modules which stores data before it is actually needed. In addition to increased operation frequencies, decreased heat production, increased latency, and increased bandwidth, the width of the prefetch buffer is increased with each successive standard of modern DDR SDRAM modules:
- DDR SDRAM's prefetch buffer width is 2-bit.
- DDR2 SDRAM's prefetch buffer width is 4-bit.
- DDR3 SDRAM's prefetch buffer width is 8-bit.
[edit] Increased Bandwidth
The speed of memory has not historically increased inline with CPU improvements.
In order to increase the bandwidth of memory modules the prefetch buffer reads data from multiple memory chips simultaneously.
This is similar to a RAID array in the storage world.
Also it is similar to the concept of Dual Channel memory - but the extra channels are internal to each module.
Sequential access bandwidth is markedly improved using prefetch buffers, but random access is mostly unchanged.
