Physical verification

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Physical verification is a process whereby an IC layout design is checked via EDA software tools to see if it meets certain criteria. Verification involves DRC(Design rule check), LVS(Layout versus schematic), ERC (Electrical Rule Check), XOR (Exclusive OR), and Antenna Checks.

Contents 1 XOR Check 2 Antenna Check 3 ERC (Electrical rule check) 4 References

[edit] XOR Check

This step involves comparing two layout databases/GDS by XOR operation of the layout geometries. This check results a database which has all the mismatching geometries in both the layouts. This check is typically run after a metal spin, where in the re-spin database/GDS is compared with the previously taped out database/GDS.

[edit] Antenna Check

Antenna checks are used to limit the damage of the thin gate oxide during the manufacturing process due to charge accumulation on the interconnect layers (metal, polysilicon) during certain fabrication steps like Plasma etching, which creates highly ionized matter to etch.

The antenna basically is a metal interconnect, i.e., a conductor like polysilicon or metal, that is not electrically connected to silicon or grounded, during the processing steps of the wafer. If the connection to silicon does not exist, charges may build up on the interconnect to the point at which rapid discharge does take place and permanent physical damage results to thin transistor gate oxide. This rapid and destructive phenomenon is known as the antenna effect.

The Antenna ratio is defined as the ratio between the physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected.

[edit] ERC (Electrical rule check)

ERC (Electrical rule check) involves checking a design for all well and substrate areas for proper contacts and spacings thereby ensuring correct power and ground connections. ERC steps can also involve checks for unconnected inputs or shorted outputs. They can also check for structures suceptible to ESD damage

[edit] References

* Clein, Dan. (2000). CMOS IC Layout. Newnes. ISBN 0-7506-7194-7