Talk:Phase-locked loop

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"might have an internal 2.4 GHz core clock which is phase aligned to a bus clock running at 100 MHz"

Isn't the 100 MHz phase-aligned to the 2.4 GHz? Hmmm... I guess not. - Omegatron 17:13, Mar 2, 2005 (UTC)

Never heard of the term phase aligned. What does it mean?--Light current 01:10, 28 March 2006 (UTC)

[edit] PC-centric bias?

I don't think an article discussing something as fundamental as phase-locked loops should start off with a fairly weird and trivial application in desktop computers. It'd be like discussing European history and starting with a list of opening dates of McDonalds' franchises in Paris. Sure, it's part of the subject but there's a *lot* going on that's more central to the topic. I'm putting this article on my to-do list but it may be a while - can someone reorganize it and mention more of the history and broad sweep of applications before obsessing on nit-picky PC guts? --Wtshymanski 17:13, 22 Apr 2005 (UTC)

**** I agree. Start with fundamentals, then bridge to specifics. -- Steve -- 00:44, 10 September 2007 (UTC)

That's just an artifact of whoever started the article and didn't know about any other applications, most likely. Fix it. :-) - Omegatron 17:39, Apr 22, 2005 (UTC)

**** Obviously. -- Steve -- 00:44, 10 September 2007 (UTC)

Actually, generating clocks for microprocessors isn't "trivial" at all. Probably the most common purpose for PLLs, actually. - Omegatron 17:41, Apr 22, 2005 (UTC)

Commonplace, sure, but not especially interesting compared to the other neat things PLLs do. I've gone through my library at home but I can't find any good history of the technique. There's got to be some rack of vacuum tubes out there that was the first PLL. --Wtshymanski 00:57, 23 Apr 2005 (UTC)

240.182

**** Correct, and should be mentioned after fundamentals. -- Steve -- 00:44, 10 September 2007 (UTC)

Yeah, I agree. That's why I started working on math fundamentals. That's how I learned. I haven't had time to get much further with it. I wanted to include simple reference solutions for common loop filters, e.g. one pole RC, lag-lead, integrator etc. I usually re-derive all the Laplace transforms every time I design one because I can't find the equations from the last time ;-) There are references out there, but most of them aren't very good. I added a couple of transforms to the Laplace transform article for just this reason. -- Madhu 23:42, 23 October 2005 (UTC)

**** This is understandable because calculating the effects of feedback is not served well by lower level math - believe me, I wish it was. As a Control Theory major in college (later an EE specializing in PLL design), it was obvious to me that simpler techniques are very inadequate and that normal (non - pole/zero, phase/gain margin, or other control theory) concepts don't help much for understanding what is going on. I struggled through the math and eventually developed a good "feel" for it. -- Steve -- 00:44, 10 September 2007 (UTC)

[edit] Time for a rewrite

The article is getting a little disorganized again and I've just pruned some apparent redundancies and added a section break. --Wtshymanski 15:03, 4 November 2005 (UTC)

[edit] PPL?

This is listed on the "PPL" disambiguation page, but "PLL" redirects here and is given in the article as the acronym. Is it also referred to as PPL sometimes, or is it just there by mistake? -Elmer Clark 07:23, 6 February 2006 (UTC)

**** I've never seen it called this. May be a common fat-finger error. Only the Phase Lock vs. Locked usage. -- Steve -- 00:44, 10 September 2007 (UTC)

[edit] Mechanical analogy

The mechanical analogy refers to a frequency locked loop- not a PLL and is therefore incorrect. This section needs rewriting explaining the phase locking operation. --Light current 21:07, 18 February 2006 (UTC)

**** Thus my comments on analogies in general. I like the marching band suggestion. -- Steve -- 00:44, 10 September 2007 (UTC)

I think the guitar tuning is a fine example. However, there should definitely be wording added to clarify how it is inaccurate. It would have confused me if I did not check the Talk page and find the discussions here. 71.245.36.73 (talk) 20:41, 19 January 2008 (UTC)

[edit] just checking

By multiplying the oscillator and the reference signals, this generates an output consisting of a low-frequency signal whose amplitude is related to the phase difference,

Should this link to beat frequency? — Omegatron 03:01, 16 April 2007 (UTC)

I wouldn't think so. Beat frequencies are what you get when you add signals together, as in tuning a guitar string with a fork. Multiplying the signals is heterodyning, which gives both high (f_A + f_B) and low (|f_A - f_B|) frequency comonents, and if you filter the high-frequency component out, leaving the difference component, it is also known as band shifting. --97.99.113.227 16:15, 5 August 2007 (UTC)

**** OOPS! It could link. I'd have to re-read that article, though.

Beat frequency _is_ a difference frequency obtained in the non linear operation of (usually) the detector (ears can also sometimes produce it) . This is due to the fact that nonlinearity of any type produces some multiplicitive effect. The Sum/Difference effect is the result of multiplication of the two signals - one signal causing some type of gain change (of the circuit) for the other signal. Simple addition of the signale will not do it. There may be some nonlinearity in the (non-ideal) adding process and therefore a beat resulting. Since tuning a guitar is a different thing altogether I think is is inappropriate here. I'd have to think about what causes instrument tuning beats - It may be a good analogy...I think there are two effects to consider there, but won't elaborate.

While I think I understand the intent of the orignal quote: "output consisting of a low-frequency signal whose amplitude is related to the phase difference" is poorly stated. For an analog PD (mixer), the "low-frequency signal" will only be present when out of lock and the frequencies not equal, thus producing the difference frequency (or beat). The Amplitude will be fixed. I *suspect* the intent was more like "When locked, the output *voltage* will be proportional to the phase difference. "

[edit] **** PD section

First describe its purpose, then *general* types, then examples of those types. Remove "An important part". _ALL_ PLL parts are important. The rest is ok, except the phase does not always have to go to zero. Type 1 loops have a constant, non zero error.

On types of PDs:

There are two major types:

1- Analog. Describe the multiplying process, sum/diff freqs, 90 degree settling point, dual requirements of the low pass filter and the resulting capture/lock range concepts. Examples, 4-Quad analog mult and double balanced diode mixer.

2- Digital. There are two subtypes.

A- The XOR, analogous to the analog types (unavoidable pun). This type is NOT fundamentally different from the above analog types and may be better placed there. It depends on how you wish to clasify them - by functionality or simply circuit type - I think here is ok. Explain that square wave inputs, or nearly so, are required and all other analog concepts apply.

B- The phase/freq (zero phase error) type. Most complex, edge triggered, Up/ Down outputs are difference between input edges, charge pump, lock detect output possible. The 4044 and its decendants.

-- Steve -- 00:44, 10 September 2007 (UTC)

[edit] OK HERE GOES GANG...

Beat freq is only important in type 0 loops like the Signetics chips where capture range and lock range are relevant factors. Those aren’t discussed so linking to beat freq isn’t appropriate. I’m not sure it is even then.

[edit] REQUEST FOR FEEDBACK.

Intro has redundancies and unneeded info. Recommended re-write of intro:

A phase-locked (or phase-lock) loop (PLL) is an electronic control system that generates a signal that is locked to the phase of an input or reference signal. This is accomplished in a common negative feedback configuration by comparing the output of a voltage controlled oscillator to the input reference signal using a phase detector. The phase detector output is then used to drive the phase of the oscillator towards that of the input reference signal.

This type of circuit is widely used in radio, telecommunications, computers and other electronic applications in order to either :

1- Generate a frequency or frequencies that is/are made as stable as some other reference frequency or

2- Detect a frequency.

This technique is widely used in modern electronic devices, with output frequencies from a fraction of a cycle per second up to many gigahertz.

2 is more than just detect frequency. I'd phrase it as "Detect a repeating reference signal in a received signal, and generate a recovered version of that reference, usually for later use as a clock for decoding the data from the received signal.

I'd add 3- Buffer a clock to one or more distant loads in such a way as to remove the phase offset caused by the propagation delay of the clock through wiring or other buffer devices. --97.99.113.227 16:23, 5 August 2007 (UTC)

OK, I like it. I'd pull these out and that that makes 4.

1- Generate freq or freqs 2- Detect freq 3- Extract clock 4- Compensate for phase skew. -- Steve -- 00:44, 10 September 2007 (UTC)

[edit] HISTORY:

Did the 1932 French paper actually propose locking the phase, or was it only the common AFC ?

What year did Signetics introduce the IC?

[edit] STRUCTURE AND FUNCTION:

Phase-lock loops can be implemented in analog or digital form.

**** Software as well. -- Steve -- 00:44, 10 September 2007 (UTC)

[edit] BLOCK DIAGRAM:

The feedback block should be generalized to just a block. It can be nothing, a divider, a programmable divider, a multiplier, a mixer or a combination of these. I believe an explanation of the effect of each of these is appropriate.

[edit] ANALOGY:

Analogies should be simpler examples that are something commonly familiar that the reader can identify with to aid in understanding the new concept. A mechanical analogy is inappropriate, I believe. The guitar tuning is ok, but, someone with basic understanding of electronics should understand the words without an analogy. A common furnace and thermostst may be a better basic control system analogy.

[edit] DIGITAL PLL

I have never seen a PLL used for a UART. Every time I run into a UART, it only divides down a reference clock to get its data clock; there is no phase-lock, VCO, or phase detector. This is why you see such interesting oscillator frequencies as 1.8432 MHz for sale (1.8432 MHz / 32 = 57.6 kbps, for example). The closest thing to a phase lock is the state machine for detecting the falling edge of the start bit, and it discards its "phase lock" information almost immediately (an error in the clock or data rate can cause the stop bit to be misinterpreted as the last data bit, or missed entirely). If anyone has an example, please give it, but I'd hardly think it was a common application.

That said, they're used all over the place in high-speed (Mbps/Gbps) serial links. But that's generally two applications: multiplying up a reference clock to the bit rate on the transmit side, and recovering the clock from the data on the received side. --97.99.113.227 16:34, 5 August 2007 (UTC)

[edit] ANALOG PLL

This should go before digital and be (as it tried to be) the general overview in more detail. This does not describe a basic PLL.

1- The U/D PD and charge pump are an advanced type. For a type 0 loop, the PD only is needed and the phase error is NOT brought to zero, but only to some fixed difference. As in the mixer or Exclusive OR PD & filter. The charge pump makes it a type 1 which does get the phase error to zero.

2- While the loop compensator does almost always have a ‘low pass’ characteristic and is frequently called as such, its primary purpose is to make the loop stable and defines its dynamic performance (lock time, lock range, pull-in range, damping, etc). It should also be noted that classical control theory methods can be used to determine loop dynamics provided the transfer functions of the individual blocks are well known.

3- The “bias generator” and “output converter” (whatever that is) are irrelevant in a basic description.

4- Again, the divide by N is also irrelevant for basics.

5- The “smooting” effect of the low pass filter is secondary to its primary purpose of determining loop dynamics. It is a "loop compensator". When spurious caused by VCO control line ‘ripple’ is a factor, then the low pass characteristics between the PD and VCO become important and often there is a trade-off between the loop dynamics and spurious. When more attenuation of spurious is needed, this can start to affect loop dynamics and more filtering usually requires slowing the loop.

**** P.S. The analog and XOR PD types have what can be considered to be excessive output ripple so that the low pass characteristics of the filter frequently greatly over-shadow the loop compensation considerations. In the complex types of PD, the loop compensating characteristics (lock time and settling characteristics) are a larger consideration and the low-pass (high frequency attenuating) characteristics become secondary, but not unimportant or trivial. -- Steve -- 00:44, 10 September 2007 (UTC)

[edit] PHASE DETECTOR:

”…such that the phase between the two inputs becomes zero.” Not generally the case. Only in type 1, and higher, Loops.

The Exclusive-OR is the digital dual of the multiplier/mixer.

I’m not familiar with the “Bang-Bang” PD.

[edit] OSCILLATOR:

Only describe a VCO and mention that there are several types. LC, crystal, SAW, Ring, digital gate, multivibrator. Should just link to full articles on those types.

”…A voltage-controlled capacitor is one method of making an LC oscillator vary its frequency in response to a control voltage….” It is the most common method. Few other methods are used.

[edit] FEEDBACK PATH:

This section should only describe the effect each type of feedback circuit has:

None : Fout = Fin.

Divide by N : Fout = N x Fin.

Multiplier : Fout = Fin / N

Programmable /N : Multiple Fout’s

Mixer : Fout = Fmix +/- Fin.

Distribution amp : Phase at all distributor outputs in phase lock.

There's also a modification to the divide-by-N feedback system that allows Fout = Fin x (N + M/A). The divide-by-N circuit is replaced with a divide-by-N-or-N+1 circuit, and another counter is used to switch in the N+1 setting for M of every A cycles. This is commonly used in radio circuits for IF generation, as it allows channels narrower than the reference oscillator, and since the reference oscillator can run faster, the loop can be made more stable. However, it can have more jitter than high-speed digital communications circuits may desire. --97.99.113.227 16:44, 5 August 2007 (UTC)

**** I stopped short of this. this can refer to the Farichild "Pulse Swollowing" or "dual Modulus" technique, or the modern more agressive and quite proprietary and complex fractional N methods (that address the issues you mention). -- Steve -- 00:44, 10 September 2007 (UTC)

[edit] JITTER:

“…called the static phase offset….” Classically called “steady state phase error”.

“… these phases…” no anticedent to ‘these’

[edit] PHASE NOISE:

It should be noted that the close-in phase noise is determined by the reference (multiplied or divided by N as appropriate) and the far out noise is that of the VCO. The cross-over frequency being determined by the loop compensator (filter) aka loop bandwidth, natural frequency, yadda, yadda.

I now see that "static phase offset" and Jitter are NOT the same thing. -- Steve --

[edit] SEE ALSO:

Why Antenna ?

Though my major was control theory, I didn’t review the math. Too long ago (:-).

It's probably not appropriate anyway because it is too complex to cover adequately here. -- Steve -- 00:44, 10 September 2007 (UTC)

Wa-Da-Ya Think ??

-- Steve -- 04:49, 20 May 2007 (UTC) = = = = = = = = = = = = …

[edit] PHASE LOCKING & MECHANICAL CLOCKS

A mechanical clock's escapement accomplishes a form of phase locking. The pendulum is the frequency reference, while the toothed wheel driven by a spring or running water is like the VCO which operates off a battery.

= = Perhaps, but you are correct with "a form of phase locking". While true, an analogy should be something quite common that is easily thought of by a reader. I think a better analogy is the common cruise control on an automobile. While more like a frequency lock loop (without knowledge if the internal circuitry it could be either), it is familiar to many people and quite similar in function ie. Frequency and speed being easily compared. = = RE: Intro

While it may not be immediately obvious, the fact that the frequency is also "controlled" is a secondary effect resulting from the relationship between phase and frequency. Therefore, it is truely phase which is measured and the frequency actually just follows. There is such a thing as an FLL (Frequency lock loop) where the frequency *is* measured/compared and the phase is not so tightly affected due to the relationship.

71.201.106.220 14:35, 17 July 2007 (UTC) That was me. -- Steve -- 14:59, 17 July 2007 (UTC)

I disagree that an escapement is a valid analogy. A Shortt master/slave clock would be, however, but that's not something many people know. One way to see that an escapement isn't a valid analogy is to see what happens if the input (the pendulum swings) stops for a moment. Answer: so does the output (the turning of the gear train). But with a PLL the output continues over gaps in the input, which is what makes clock recovery possible. Paul Koning 20:34, 18 July 2007 (UTC)

I was not comfortble with the clock. I was thinking the escapement wheel was locked to the pendulum with the number of teeth being like a divide by N, but thought it was a stretch. On the other hand, the fact that the PLL dVCO oesn't Actually "stop" is only the result that the specific implememtation lf a VCO doesn't allow it to go to zero freq. If it could, it would follow the reference frequency down to zero, in some of the types. (only an irrelevant nit, though)-- Steve -- 00:44, 10 September 2007 (UTC)

[edit] A real world analogy

For an analogy that's familiar and more accurate than the FLL "tuning an instrument" one -- consider marching to the beat of a drum. The marchers are the VCO, the drum is the reference input. And just like in clock recovery, if the drum misses a beat, the marchers will keep marching. Paul Koning 20:36, 18 July 2007 (UTC)

Paul, I like the marching band, but the "miss a beat concept", as you explain, is somewhat "clock-recovery centric", so to speak, because that is one of its important characteristics and is imphasized during clock recovery design. This characteristic is secondary (thought not UNdesirable) in other uses. Missing a beat in a frequency synthesizer will produce an undesirable spike, depending on the loop characteristisc, while it will be minimized to some extent, is not usually a consideration in its design. This may be viewed as a rather fine point, but that is my slant.

I was intimidated by the magnitude of the required editing. There's a lot in there which can stay, but re-org and generalization is necessary. I'm also glad to see other comments here. I've inserted more comments above, marked with ****...

[edit] Proposal

With all these good comments and so much to fix, unless someone DOES something, it'll not happen. I propose that you (whomever) just Pick either a section or the overall outline and change it. Then we can work on those changes. I'll take the first move and re-do the intro, per my above, and wait for the flack. Regards, -- Steve -- 00:44, 10 September 2007 (UTC)

Numbered lists should indicate priority. I would strongly recommend avoiding numbered lists in the lead paragraph of the article. I agree that the block diagram has a few elements that are not explained in the description of operation. Perhaps you can explain Type 0, Type 1, loops and the significance of the types. References are always good. --Wtshymanski 16:05, 17 September 2007 (UTC)

Would an unnumbered list be appropriate? Explanation of feedback system 'type' belongs in Control Theory, which I see it is not. -- Steve -- 03:33, 23 September 2007 (UTC)

[edit] Bad analogy moved here

[edit] Analogy

Tuning a string on a guitar can be compared to the operation of a phase-locked loop. Using a tuning fork or pitchpipe to provide a reference frequency, the tension of the string is adjusted up or down until the beat frequency is inaudible. This indicates that the tuning fork and guitar are vibrating at the same frequency. If we imagine the guitar could be tuned perfectly to the reference tuning fork frequency, and maintained there, the guitar would be said to be in phase-lock with the fork.

I removed that irrelevant See also: antenna -- Steve -- 03:23, 23 September 2007 (UTC)

Restored the absolutely relevant analogy. Guitar tuning is even done for a simlar reason to use a PLL - to adjust a variable oscillator to an accurate reference. --Wtshymanski 19:42, 23 September 2007 (UTC)

Perhaps you misinterpreted. I removed the reference to Antenna, not guitar tuning. That may have been Paul. I was uncomfortable with it, but upon further thinking, if walking down a winding path can be an analogy of a human feed back system, then instrument tuning can also.-- Steve -- 06:12, 18 October 2007 (UTC)

[edit] DPLL section nearly completely wrong

Clock synthesizers for microprocessors are almost always analog PLLs. The whole point is to multiply the frequency to well above the crystal frequency. To do that with a DPLL, you'd need an extremely high frequency clock source to run the DPLL, and that would defeat the purpose.
As someone else observed above, UARTs don't use PLLs, as they are asynchronous. PLLs are used for clock recovery in many synchronous data communication systems, but those aren't UARTs.
The claim that "The phase detector may be a simple comparator" is so unclear as to be useless. What kind of comparator? A magnitude comparator? What is it comparing?
The claim that "much of a digital PLL may be implemented using even a very small" PAL is wrong or at least misleading, and basically irrelevant. A very small PAL is something like a 16V8, 20V8, or 22V10, and you can't get a substantial part of any practical DPLL into one. Even if your counters only have four-bit resolution, That uses 8 of the 10 available macrocells in the 22V10, which doesn't leave enough for the control logic. A more modern CPLD with 32 or more macrocells may be suitable, but technically that isn't a "small PAL".

Given that the DPLL section is riddled with errors and the information that isn't outright incorrect is misleading, the section needs to be either completely rewritten or eliminated. --Brouhaha (talk) 22:17, 29 December 2007 (UTC)