Talk:Pentium Pro
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Is it worth replacing the current image with one of mine from here? --CTho 17:44, 18 December 2005 (UTC)
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[edit] Cleavage
I'm not ready to tackle the main text at this time. I wish for now to point out that the article as presently written fails to capture the Pentium Pro for its watershed significance. It wasn't a much loved chip in the broad market. However, for those of us who were observed the events sharply, it's introduction announced the beginning of the end of the tired RISC vs CISC debate. I recall the RISC camp was shocked and consternated by the SPEC numbers reported for the early silicon. It was the age old mistake of failing to distinguish representation from model. The x86 binary instruction set is terribly wonky representation with a broad assortment of quirks and disadvantages, not all of which played out as badly as many people at first assumed. However, the x86 instruction set contains within it, more or less as a proper subset, very nearly the whole of the RISC instruction set execution model and this conceptual subset is what became known as the micro-op execution engine, which first saw the light of day as the Pentium Pro.
[edit] Hot Blob
The conceptual cleavage of representation (binary instruction set) from model (micro-op execution primitives) did turn out to exact a cost in another performance metric: heat. The on-the-fly mapping between the two worlds introduces a big blob of hot running transistors that a pure RISC processor doesn't require. You gain part of this effect back in a strange way. The hot blob also acts as an on-the-fly decompression engine from the more compact x86 instruction encoding as compared to the more bloated (and uniform) RISC encoding. However, this magnifies the net capacity of the L1 instruction cache, an effect proportional to the size of cache provided, whereas the hot blob remains more or less constant size, and shrinks in relative significance as the chp density increases. A 16KB L1 icache on the P6 core holds as many instructions as a 24KB L1 cache on most of its RISC competitors (typically an 8/5 ratio). At that stage your hot blob is worth another 8KB of cold icache. But then when the L1 icache expands to 64KB, the exact the same hot blob is now equivalent to adding another 32KB of cold icache, and maybe it's now smaller as well (though I don't know the die size numbers off hand).
In the P4 era, Intel recognized another problem: the hot blob was creating decode latency problems and this observation lead to the netburst architecture, where the icache contains predecoded instruction traces (at great cost in bloat), but you continue to pay the price of the hot blob whenever the icache is updated with new instruction traces.
When WindowsNT was recompiled for the IBM-Apple Power archicture (the mostly failed CRP) all the binaries bloated by 40% And since disk space was still costly and system memory even more so, very little of the theoretical RISC advantage materialized. Flash forward to 2006 where memory and disk are cheap as dirt, most would gladly trade the extra disk and memory to eliminate 40W of processor heat. But that was not the deal then. The unwinding of that initiative is one of several events which later opened the door for Steve Jobs to return to Apple.
Transmeta was almost a pure play in taming the hot blob. Instead of translating the x86 instructions on-the-fly into a trace cache, the translation is done into a larger chunk of system memory onto some architecturally hidden instruction set more ideally suited to power-efficient execution.
AMD took yet another stance: learn to live with it more or less as it comes. I'm fairly certain they expand the x86 instructions with "hint bits" (which does bloat your icache cost) sufficient to eliminate decode latency problems when the instructions are later consumed. This delves deeply into the domain of trade-secrets since it is almost entirely concealed from the layers above.
[edit] Long Live the King
Here's another small detail: the P6 core scaled from introduction at 200MHz up to almost 1GHz with the last gasp of the Pentium III (as I recall, the 1.133GHz chip Intel did briefly produce was mostly a joke) better than a 5:1 range (not even counting the Tualatin derivatives up to 1400MHz). The Pentium IV was introduced at 1.4GHz and scaled to 3.8GHZ (with major issues) a ratio of 2.7:1 before the world sproinged in the multicore direction. The effective scaling range of the Pentium was 90MHz to 266MHz. The 60MHz 5V core was never taken seriously, and the 300MHz version was an afterthought.
So let's grant the Pentium Pro some respect. It was the first king in a monarchy that scaled over a 7:1 range if you rope in Tualatin, wider than any other Intel core technology I can think of. It was also the technology that consigned Windows 98 to the dust bin, so let's forget that either. And it established Intel as a serious player in the commodity x86 server space just in time to catch the leading edge of the dotcom boom. I weary of the Pentium Pro being viewed historically as an "odd duckling". You just had to look a little more closely than normal to see history in the making.
- "It was also the technology that consigned Windows 98 to the dust bin"
- do you have any evidence for that claim? By the time XP (the first NT based os to be marketed to normal users) was released netburst was already on it's way in. Many many PII and PIII systems were sold with 98 or ME on them. Plugwash (talk) 09:52, 28 March 2008 (UTC)
[edit] I don't get no respect
Contrast this to the Sony/IBM Cell processor, which is far more of an "odd duckling" relative to design tradition than the Pentium Pro ever was. Yet it seems to earn more implicit respect for being an "abrupt transition" than the Pentium Pro did for ringing in an entirely non-disruptive 7:1 performance scaling.
I like the Cell myself, I am working in that area now. However, I regard the Pentium Pro as at least its equal in historical significance to how the architecture landscape played out. The history on this point is clouded by the number of people running around after the PPro introduction complaining that the sky didn't fall as planned entirely to schedule. Many people implicityly regarded the PPro as bringing the much unloved vampire back from the grave with seemingly eternal life. It was a major blow for Wintel against Sun whose Sparc chips were long in recovering their edge in any area other than floating point and aggregate system bandwidth (the later is largely a cost of implementation issue: more pins, more bandwidth, more cost; having not so much do to with good genes, good breeding, blue blood, or right thinking virtue).
- I think you're confusing the Pentium Pro and the P6 architecture. The Pentium Pro didn't scale 7:1, the P6 architecture did. Also, I think you hit the nail on the head. The Cell get's respect because it is such an odd beast that some people think it might be somehow useful. The P6 was more evolutionary and it did command a lot of respect even if the Pentium Pro iteration of it didn't get so much for a variety of reasons Nil Einne 23:03, 23 July 2007 (UTC)
[edit] Dithering
I'm still somewhat new to the Wikipedia, so I don't know how much bias there is toward reporting the blandly verifiable over capturing the impact of note within the context of its day. I'll have to give this some thought and return some other time.
I know that's somewhat screedish in the way I blorped it out. Anyone else have opinions on what prominence prominence deserves for the main text? MaxEnt 23:37, 4 April 2006 (UTC)
- WP:Verifiability and WP:NPOV are absolute and non negotiable even if it makes the article seem bland for you. Also, talk pages aren't the place for you to post your opinions of a subject either but to discuss how to improve the article. Nil Einne 23:05, 23 July 2007 (UTC)
[edit] Math bug in the Pentium Pro and Pentium II
Why is there no mention of the "Flag Erratum" reported by Robert R. Collins?
- Who knows? You can always add it yourself. —BorgHunter
ubx(talk) 01:43, 8 May 2006 (UTC)- And please sign your questions it's considered good form. MaxEnt 02:46, 2 June 2006 (UTC)
[edit] Stunningly Enormous
Someone bothered by the unprofessional tone edited enormous socket 8 to large socket 8 which I just changed to stunningly large socket 8. It was stunning for the day. There were already large chips, but this was a monster that no-one anticipated. MaxEnt 02:46, 2 June 2006 (UTC) The Math bug was on the Pentium 60 chip only I thought?
[edit] Alpha as a competitor
Should not the Alpha CPU be added along the list of competitors to the Pentium Pro? It was at the time the fastest available processor and a strong competitor in the pro-market. The Cyrix and IDT Winchip was IMHO never competitors to the Pentium Pro since they didn't fought for the same part (the the pro/workstation) of the market. I'm not to sure about the Pentium and K5 as well. While the performance difference wasn't that great between the PPro, Pentium and K5 the available chipsets made a larger impact in defining "consumer-cpu" and "professional cpu" with regard to memory support etc. 81.233.73.177 18:06, 17 February 2007 (UTC)/Håkan 2007-02-17
- I agree that they were competitors to a point, however DEC Alphas were vastly higher end. Pentium Pros tended to be marketed more to the 'enthusiast' home and small business market. SPARC and Alpha had more parity, however the emergence of the Pentium Pro foreshadowed the role that cheap x86 server hardware would have in undermining the high end proprietary UNIX/VAX server market. --Bk0 (Talk) 22:27, 17 February 2007 (UTC)
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- Maybe you're correct, I ventured back to my computer magazines from -96 and the Pentium Pro was primarily sold in desktops and workstations while the Alpha was sold in high-end workstations and larger servers. I don't think OTOH that the enthusiast market showed much interest in the PPro since it was replaced by the faster PII before prices on motherboards and processors had fallen to a level low enough to attract that crowd. 81.233.73.177 12:14, 18 February 2007 (UTC) /Håkan 2007-02-18
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- Oh I think it definitely had enthusiast appeal. Computer Gaming World always promoted the PPro, prior to "superior" alternatives like PII. They used it in their ultimate game machine. They also snubbed the competing AMD K5/K6 and especially Cyrix CPUs as almost worthless for gamers. A friend of mine in high school went PPro back then too. It was great for the DOS 3D games of the day, especially flight sims (which he played a lot of). I was following PPro the day it hit the market. But it was expensive, for sure. Still, it was undeniably the best x86 CPU of the time, if also the priciest. I would've gone PPro myself if I'd been buying at the time, but I ended up with a "klamath" Pentium II 233 as an upgrade from 486-class hardware. It wasn't cheap at all, either, being around $600.
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- It is tough to say just what PPRO competed with. It wasn't high end server, but it was used for servers for sure. Its x86 pals weren't in the same class either. It was almost alone, really. It was obviously a generation ahead, but that didn't get leveraged until years later. Pentium MMX was certainly a desktop competitor, because its performance rivaled PPRO. And K6 was too, until you looked at FPU, the awful platform, and instruction set. --Swaaye 20:29, 18 February 2007 (UTC)
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[edit] Recent image change
I think the old image (removed by http://en.wikipedia.org/w/index.php?title=Pentium_Pro&diff=119762634&oldid=116442684 on April 2) was better than the current one. Comments? --CTho 00:38, 3 April 2007 (UTC)
[edit] Multi-Chip Module
Pentium Pro is the first Intel MCM CPU (or even chip), isn't it? If so, can someone add this fact to the article?
BTW, the caption of an image in the article reads "Uncapped Pentium Pro underside (256/512)". What does 256/512 mean? Warut (talk) 06:15, 6 January 2008 (UTC)
- Yes, I believe the Pentium Pro is Intel's first MCM CPU. As for the caption, 256/512 refers to the amount of L2 cache the CPU had. It should be really clarified. Rilak (talk) 07:45, 6 January 2008 (UTC)
- Thanks, Rilak. It is stated in the image page that this CPU is 200MHz with 256KB of L2 cache. So could 256/512 be in fact 200/256? Warut (talk) 12:33, 13 January 2008 (UTC)
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- Not exactly. Sorry, I should have clarified. Pentium Pros with 256 and 512 KiB of L2 cache have a similar appearance, with the processor die on the left and the cache die on the right. The caption reads 256/512 because whoever wrote that caption believed the same picture was relevant to models with 256 and 512 KiB of L2 cache. However I don't believe that this is correct as I think that the 512 KiB cache die was produced in a different process, (35 micron vs .5 micron for the original 256 KiB cache die) and that would have lead to a slightly different appearance. Anyways, I've fixed the caption to match the info in the image description. Rilak (talk) 12:54, 13 January 2008 (UTC)
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[edit] Misleading?
I just did a quick read of this article and noticed that some statements are misleading.
For example, the article states, "The core of Pentium Pro featured several new technologies, including: speculative execution, superpipelining, an advanced L2 cache, register renaming, out of order execution, and a wider 36-bit address bus (usable by PAE)."
This statement I believe are misleading - some of these technologies were featured in CPUs that predate the Pentium Pro. For example, superpipelining was present in CPUs such as the MIPS R4000 and the MIPS R4400, both released significantly before the Pentium Pro. Register renaming and out of order execution was featured on the IBM POWER2 (1993) to a limited degree and the PowerPC CPUs. The importance of the 36 bit is perhaps overstated, as CPUs such as the Alpha 21064 (1992) had a 34 bit address bus and the Alpha 21164 (1995) had a 40 bit address bus. It should also be noted that the Alpha 21164 predated the Pentium Pro by a many months. Perhaps the statement should clarify that these features were 'new' in the x86 family.
"At the time, manufacturing technology did not feasibly allow L2 cache to be integrated into the processor core." - This statement I believe is also misleading. The Alpha 21164 (1995) placed a 96 KiB L2 cache on the die. Perhaps the statement should be revised to, "At the time, manufacturing technology did not feasibly allow a large L2 cache to be integrated into the processor core."
"The two dies — both of which were very large by the standards of the day..." - This statement is also misleading. It gives the impression that the two dies where much larger than those of the same period, but looking at the Alpha 21164 (1995) with a die size of 16.9 x 18.6 mm, compared to the Pentium Pro's die size of 17.5 x 17.5 mm, suggests that the Pentium Pro's die size was average for that period. Also, consider the Sun UltraSPARC (1995), with a die size of 315 mm2 and the MIPS R10000 (early 1996) with a die size of 299 mm2.
As for this statement, "Although only advertised as supporting dual-processor operation, it was capable of running in four- or six-CPU configurations." - It is entirely false. According to Intel's support page regarding this issue it states: "The Pentium® II OverDrive® processor is capable of multiprocessor support up to 2-way multiprocessing, or 2MP." The original page can be found here: http://www.intel.com/support/processors/overdrive/sb/cs-013307.htm
Any comments? Rilak (talk) 10:41, 6 January 2008 (UTC)
[edit] MMX
Don't some or all of the Pentium Pros have MMX support? 74.139.89.19 (talk) 01:25, 12 February 2008 (UTC)
[edit] MiB and KiB v.s. MB and KB
Note. For interested authors, debate and a vote is ongoing on Talk:MOSNUM regarding a proposal that would deprecate the use of computer terms like “kibibyte” (symbol “KiB”), “mebibyte” (symbol “MiB”), and kibibit (symbol “Kib”). It would no longer be permissible to use terminology like a “a SODIMM card with a capacity of two gibibytes (2 GiB) first became available…” and instead, the terminology currently used by manufacturers of computer equipment and general-circulation computer magazines (“two gigabytes, or 2 GB”) would be used. Voting on the proposal is ongoing here. Greg L (my talk) 21:15, 27 March 2008 (UTC)
- Sounds like a boatload of fun. I'm not changing what work I've already done. Someone else can change it. Also, pushing something to a vote and working off of that decision is not the same as discussing it and coming to the best conclusion.--MARQUIS111 (talk) 21:04, 30 March 2008 (UTC)
