Network On Chip

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Network-on-a-chip (NoC) is a new approach to System-on-a-chip (SoC) design. NoC-based systems can accommodate multiple asynchronous clocking that many of today's complex SoC designs use. The NoC solution brings a networking method to on-chip communication and brings notable improvements over conventional bus systems.

1 Emerging Paradigm
2 Parallelism and Scalability
3 Benefits of Adopting NoCs
4 Research on On-chip Networks
5 References
6 See also

[edit] Emerging Paradigm

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology." In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. An NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. An NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on "application-specific NoC topology synthesis".

[edit] Parallelism and Scalability

The wires in the links of the NoC are shared by many signals. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, an NoC provides enhanced performance (such as throughput) and scalability in comparison with previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Of course, the algorithms must be designed in such a way that they offer large parallelism and can hence utilize the potential of NoC.

[edit] Benefits of Adopting NoCs

The adoption of NoC architecture is driven by several forces: from a physical design viewpoint, in nanometer CMOS technology, interconnects dominate both performance and dynamic power dissipation, as signal propagation in wires across the chip requires multiple clock cycles. NoC links can reduce the complexity of designing wires for predictable speed, power, noise, reliability, etc., thanks to their regular, well controlled structure. From a system design viewpoint, with the advent of multi-core processor systems, a network is a natural architectural choice. An NoC can provide separation between computation and communication, support modularity and IP reuse via standard interfaces, handle synchronization issues, serve as a platform for system test, and, hence, increase engineering productivity.

[edit] Research on On-chip Networks

Although NoCs can borrow concepts and techniques from the well-established domain of computer networking, it is impractical to blindly reuse features of "classical" computer networks and symmetric multiprocessors. In particular, NoC switches should be small, energy-efficient, and fast. Neglecting these aspects along with proper, quantitative comparison was typical for early NoC research but nowadays they are considered in more detail. The routing algorithms should be implemented by simple logic, and the number of data buffers should be minimal. Network topology and properties may be application-specific. NoCs need to support quality of service, namely achieve the various requirements in terms of throughput, end-to-end delays and deadlines. To date, several prototype NoCs have been designed and analyzed in both industry and academia (see materials of the 2006 full-day workshop on NoCs) but only few have been implemented on silicon. However, many challenging research problems remain to be solved at all levels, from the physical link level through the network level, and all the way up to the system architecture and application software. The first dedicated research symposium on Networks on Chip was held in Princeton, NJ, in May 2007. Now, you can find the presentation slides at the NOCS 2007 website.

[edit] References

M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, A. Sangiovanni, Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design, DAC, 2001, pp. 667 -672.
Jantsch, J. Oberg and H. Tenhunen (Eds.), Journal of System Architecture, special issue on networks on chip, Volume 50, Issues 2-3, Pages 61-168 (February 2004).
L. Benini (Ed.), Integration . the VLSI journal, special issue on networks on chip, Volume 38, Issue 1, Pages 1-130 (October 2004).
A. Jantsch and H. Tenhunen (Eds.), "Networks on Chip," Kluwer Academic Publishers, 2003.
E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "QNoC: QoS architecture and design process for cost-effective Network on Chip," The Journal of Systems Architecture, Volume 50, pp. 105-128, February 2004.
E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny , "Cost considerations in Network on Chip," Integration - the VLSI journal, Vol. 38, No. 1, pp. 19-42, Oct. 2004.
L. Shang, L.-S. Peh, A. Kumar and N. K. Jha, "Thermal-aware on-chip networks", IEEE Micro Top Picks of Architecture Conferences, Jan.--Feb. 2006
H. Wang, L.-S. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks", In Proceedings of the 36th International Symposium on Microarchitecture, Nov. 2003.
X.-T. Tran, J. Durupt, F. Bertrand, V. Beroulle, and C. Robach. "A DFT Architecture for Asynchronous Networks-on-Chip". In Proceedings of the 11th IEEE European Test Symposium (ETS'06)/, May 2006.
NoC 2006
On-Chip Networks Bibliography
Benini, L.; De Micheli, G. , Networks on chips: a new SoC paradigm, Computer , Vol. 35, Iss. 1, January 2002, pp. 70 -78.
Research bibliography at OCP-IP web site <
Interconnect-Centric Design for Advanced SoC and NoC, Jari Nurmi, Axel Jantsch, Hannu Tenhunen, and Jouni Isoaho (eds.), Kluwer Academic Pub, August 2004
Benini, L. ; De Micheli, G., Networks on Chips: Technology and Tools, Morgan Kaufmann, 2006.
Cristian Grecu, Andrè Ivanov, Partha Pande, Axel Jantsch, Erno Salminen, Umit Ogras, Radu Marculescu, An Initiative towards Open Network-on-Chip Benchmarks, OCP-Ip white paper, 2007, [Online] http://www.ocpip.org/socket/whitepapers/NoC-Benchmarks-WhitePaper-15.pdf
D. Borrione, A. Helmy, Pr. Laurence Pierre, J. Schmaltz: "A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study". Proc. ACM/IEEE International Symposium on Networks-on-Chips (NOCS'2007), May 2007. IEEE Computer Society Press