NCSim
From Wikipedia, the free encyclopedia
NcSim | |
---|---|
Developed by | Cadence Design Systems |
Latest release | insert_version / insert_release_date |
OS | Cross-platform |
Genre | Simulator |
License | subscription |
Website | http://cadence.com |
Incisive is a suite of tools from Cadence Design Systems related to design and verification of ASICs, SOCs, and FPGAs. Incisive is commonly referred to by the name NCSim in reference to the core simulation engine. In the late 1990s, this tool suite was formerly known as "ldv" which stands for 'logic design and verification'.
Depending on the design requirements, incisive has many different bundling options of the following tools:
Tool | command | description |
---|---|---|
NC Verilog | ncvlog | native compiler for verilog 95, verilog 2001 and System Verilog |
NC Vhdl | ncvhdl | native compiler for vhdl 87, vhdl 93 |
NC System C | ncsc | native compiler for systemC |
NC Elaborator | ncelab | unified linker/elaborator for verilog, vhdl, and systemc libraries. generate a simulation object file referred to as a snapshot image. |
NC Sim | ncsim | unified simulation engine for verilog, vhdl, and systemc. loads snapshot images generated by NC Elaborator. this tool can be run in gui mode or batch command line mode. In gui mode, ncsim is similar to the debug features of modelsim's vsim. |
Sim Vision | simvision | a standalone graphical waveform viewer and netlist tracer. this is very similar to Novas Software's debussy. |
[edit] See also
- Modelsim
- List of Verilog Simulators