Minimal instruction set computer
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Minimal Instruction Set Computer (MISC) is a processor architecture with a very small number of basic operations and corresponding opcodes. Such instruction sets are commonly stack based rather than register based to reduce the size of operand specifiers. Such a stack machine architecture is inherently simpler since all instructions operate on the top most stack entries. A result of this is a smaller instruction set, a smaller and faster instruction decode unit, and overall faster operation of individual instructions. The downside is that instructions tend to have more sequential dependencies, reducing instruction-level parallelism. MISC architectures have a lot in common with the Forth programming language, and the Java Virtual Machine.
Probably the most commercially successful MISC was the INMOS transputer.
[edit] See also
- Complex instruction set computer (CISC)
- Reduced instruction set computer (RISC)
- Zero Instruction Set Computer (ZISC)
[edit] External links
Related websites
- Forth MISC chip designs
- seaForth-24 - the latest multi-core MISC design from Chuck Moore
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