List of Verilog simulators
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Verilog simulators are software packages that emulate the Verilog hardware description language. Verilog simulation software has come a long way since its early origin as a single proprietary product offered by one company. Today, Verilog simulators are available from many vendors, at all price points. For desktop/personal use, Aldec, Mentor, LogicSim, SynaptiCAD, and others offer reasonably priced (<$5000 USD) tool-suites for the Windows 2000/XP platform. The suites bundle the simulator engine with a complete development environment: text editor, waveform viewer, and RTL-level browser. Additionally, limited-functionality editions of the Aldec and Modelsim simulator are downloadable free of charge, from their respective OEM partners (Actel, Altera, Lattice Semiconductor, Xilinx, etc.) For those desiring open-source software, there is Icarus Verilog, among others.
Beyond the desktop level, enterprise-level simulators offer faster simulation runtime, more robust support for mixed-language (VHDL and Verilog) simulation, and most importantly, are validated for timing-accurate (SDF-annotated) gate-level simulation. The last point is critical for the ASIC tapeout process, when a design-database is released to manufacturing. (Semiconductor foundries stipulate the usage of tools chosen from an approved list, in order for the customer's design to receive signoff status. Although the customer is not required to perform any signoff checking, the tremendous cost of a wafer order has generally ensured thorough design-validation on the part of the customer.) The three major signoff-grade simulators include Cadence Incisive (NC-Verilog), Mentor Modelsim/SE, and Synopsys VCS. Pricing is not published publicly, but all three vendors are known to charge $25,000-$100,000 USD per seat, 1-year time-based license.
FPGA vendors do not require expensive enterprise simulators for their design flow. In fact, most vendors include an OEM version of a third-party HDL simulator in their design suite. The bundled simulator is taken from an entry-level or low-capacity edition, and bundled with the FPGA vendor's device libraries. For designs targeting high-capacity FPGA, a standalone simulator is recommended, as the OEM-version may lack the capacity or speed to effectively handle large designs.
Below is a list of simulators that implement the Verilog hardware description language:
Contents |
[edit] Commercial Simulators
| Simulator Name | Author/Company | Languages | Description |
|---|---|---|---|
| Active-HDL, Riviera | Aldec | VHDL-2002, V2001, SV2005 | A simulator with complete design environment well suited for FPGA-applications. Aldec licenses Active-HDL to FPGA-vendors, and the underlying engine can be found in the design-suites of those vendors. While ActiveHDL is a low-cost product, Aldec also offers a more expensive, higher-performance simulator called "Riviera." |
| ISE Simulator | Xilinx | VHDL-93, V2001 | Xilinx's simulator comes bundled with the Foundation ISE design suite. Although limited to simulating designs targeted for Xilinx's own FPGAs, ISE Simulator is one of the least expensive simulators, although lacking the mixed-HDL capability. |
| LogicSim | Zeemz | V2001 | Recently introduced, this low-cost simulator only runs on Microsoft Windows. |
| ModelSim ('big 3') | Mentor Graphics | VHDL-2002, V2001, SV2005 | The original Modeltech (VHDL) simulator already commanded a loyal userbase, and attracted many new users with the first mixed-language simulator capable of simulating VHDL and Verilog design entities together. In the FPGA market Modelsim/PE currently enjoys number 1 position. As one of the 'big 3' simulators Modelsim/SE is qualified for ASIC (validation) sign-off at nearly all semiconductor fabs. |
| NC-Verilog/Incisive ('big 3') | Cadence Design Systems | VHDL-2002, V2001, SV2005 | In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. Like its predecessor Verilog-XL, NC-Verilog held a dominant position in industry for many years, largely due to outstanding performance in timing-annotated gate (netlist) simulation. But Synopsys's VCS, bolstered by the acquisition of Superlog and quick deployment of Systemverilog support, overtook NCsim in many ASIC-design companies. The modern version of NCsim, called Incisive, boasts some unique features (such as e-Verification language support) and a fast SystemC simulation kernel, although VCS remains the leader in Systemverilog. As one of the 'big 3' simulators, Incisive is qualified for ASIC (validation) sign-off at nearly all semiconductor fabs. |
| PureSpeed | Frontline | V1995 | The simulator had a revenue of up to $7 million at one time (1995). Famed by its 'regional cycle-based' simulation concept. It has a cycle-based counterpart called 'pure cycle'. FrontLine was sold to Avant!, which was later acquired by Synopsys. Synopsys discontinued Purespeed in favor of its well-established VCS simulator. |
| QuartusII Simulator | Altera | Altera's simulator bundled with the Quartus II design software. Supports Verilog, VHDL and AHDL. | |
| SILOS | Simucad Design Automation | V2001 | As one of the low-cost Verilog simulators, Silos III enjoyed great popularity in the 1990s. Simucad's most current version, Silos-X, is sold as part of a tool-suite. |
| Super-FinSim | Fintronic | V2001 | This simulator is available on multi-platform, claiming IEEE 1364-2001 compliant. |
| VCS ('big 3') | Synopsys | VHDL-2002, V2001, SV2005 | Originally developed by John Sanguinetti, Peter Eigenburger and Michael McNamara under the startup company Chronologic Simulation, VCS (Verilog Compiled code Simulator) was purchased by Synopsys, where development continued. Synopsys's continual investment in simulation technology has resulted in VCS overtaking Cadence's NC-Verilog as the #1 Verilog/Systemverilog simulator at Fabless-ASIC companies. Due to a strategic decision to support Systemverilog (instead of SystemC), and the timely acquisition of Superlog (the forerunner to Systemverilog), Synopsys/VCS was able to capture a commanding lead in Systemverilog simulation market. As Systemverilog has grown to become a more significant part of the overall HDL market, VCS continues to hold its #1 position. As one of the 'big 3' simulators, VCS is qualified for ASIC (validation) sign-off at nearly all semiconductor fabs. |
| Verilogger Extreme, Verilogger Pro | SynaptiCAD | V2001,V1995 | Verilogger Pro is a low-cost interpreted simulator based on Elliot Mednick's VeriWell code base. Verilogger Extreme is a newer, compiled-code simulator that is Verilog-2001 compliant and much faster than Pro. |
| Verilog-XL | Cadence | V1995 | The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. Cadence recommending NC-Verilog for new design projects, as XL no longer receives active development. Nevertheless, XL continues to find use in companies with large codebases of legacy Verilog. Many early Verilog codebases will only simulate properly in Verilog-XL, due to variation in language implementation of other simulators. |
| Veritak | Sugawara Systems | V2001 | It is low-cost and Windows-based only. It boasts a built-in waveform viewer and fast execution. |
Some commercial simulators (such as Modelsim) are available in student, or evaluation/demo editions. These editions generally have many features disabled, arbitrary limits on simulation design size, but are offered free of charge.
[edit] Open-source Simulators
| Simulator Name | Author/Company | Supported Languages | Description |
|---|---|---|---|
| GPL Cver | Pragmatic C | V2001 | This is a GPL open-source simulator with many performance features turned off. These features can be enabled for a fee. It is a pure simulator. |
| Icarus Verilog | Stephen Williams | V2001 | This simulator is not fully IEEE compliant. |
| Verilator | Veripool | V2001, V2005, minimal SV2005 | This is a very high speed open-source simulator that compiles synthesizable Verilog to C++/SystemC. |
| VeriWell | Elliot Mednick | V1995 | This simulator used to be commercial, but has recently become GPL open-source. Compliance with 1364 is not well documented. It is not fully compliant with IEEE 1364-1995. |
[edit] Key
| Tag | Description |
|---|---|
| V1995 | IEEE Verilog 1364-1995 |
| V2001 | IEEE Verilog 1364-2001 |
| V2005 | IEEE Verilog 1364-2005 |
| SV2005 | IEEE SystemVerilog 1800-2005. Note: Although Systemverilog-2005 is a superset of Verilog-2005, few Systemverilog simulators explicitly support Verilog-2005's new features. |
| VHDL-1987 | IEEE VHDL 1987 |
| VHDL-1993 | IEEE VHDL 1993 |
| VHDL-2002 | IEEE VHDL 2002 |
