List of AMD CPU microarchitectures

From Wikipedia, the free encyclopedia

This article may not meet the general notability guideline or one of the following specific guidelines for inclusion on Wikipedia: Biographies, Books, Companies, Fiction, Music, Neologisms, Numbers, Web content, or several proposals for new guidelines. If you are familiar with the subject matter, please expand or rewrite the article to establish its notability. The best way to address this concern is to reference published, third-party sources about the subject. If notability cannot be established, the article is more likely to be considered for redirection, merge or ultimately deletion, per Wikipedia:Guide to deletion.
This article has been tagged since October 2007.

The following is a list of AMD CPU microarchitectures.

This list is incomplete; you can help by expanding it.

1 x86 microarchitectures
2 Other microarchitectures
3 References
4 See also
5 External links

[edit] x86 microarchitectures

K5 microarchitecture - AMD's first original microarchitecture. The K5 was based on the AMD Am29000 microarchitecture with the addition of an x86 decoder. Although the design was similar in idea to a Pentium Pro, the actual performance was more like that of a Pentium.
K6 microarchitecture - The K6 was not based on the K5 and was instead based on the Nx686 processor that was being designed by NexGen when that company was bought by AMD. The K6 was generally pin compatible with the Intel Pentium (unlike NexGen's existing processors).

K6-2 microarchitecture - An improved K6 with the addition of the 3DNow! SIMD instructions.
K6-III microarchitecture - A further improved K6 with three levels of cache -- 64KB L1, 256KB full-speed on-die L2, and a variable (up to 2MB) motherboard mounted L3.

K7 microarchitecture - Microarchitecture of the AMD Athlon and Athlon XP microprocessors. Was a very advanced design for its day.
K8 microarchitecture - Also called Hammer (its AMD internal codename), or SledgeHammer (after the first die in the Hammer family). The K8s central processor unit is based on the K7 but was extended to 64-bits, added an integrated memory controller, HyperTransport communication fabric, L2 cache sizes up to 1 MB (1128 KB total cache), and SSE2. Later K8 added SSE3. The K8 was the first mainstream Windows compatible 64-bit microprocessor and was released April 22, 2003. K8 replaced the traditional front side bus with a HyperTransport communication fabric.
- Dual core K8 - The dual core Athlon 64 X2 was sometimes incorrectly referred to as the K9 by the press after the cancellation of the original K9 (see below).
K9 microarchitecture - Canceled ^[1] microarchitecture rumored to have been an 8-issue, multi-threaded processor using DDR2 memory to compete with the Intel NetBurst architecture. A few parts of the K9 design were salvaged and used in the K8 revision F/G processors.
K10 microarchitecture - Also incorrectly called K8L in the press, or Barcelona (after the first processor using this microarchitecture) the AMD Family 10h microarchitecture is a new architecture with native quad core, shared level 3 cache, 128-bit floating point units, AMD-V Nested Paging virtualization, and HyperTransport 3.0.
Griffin microarchitecture - Griffin is designed solely for mobile platforms and will be the successor to Turion 64. Griffin will be released with the Puma platform in 2008. Griffin is based on 65nm K8 revision G with power optimization technologies specific to the demands of the mobile market. In face the Griffin power optimizations are beyond those in the AMD Family 10h microarchitecture.
Bulldozer processor core - A microprocessor core after the K10 microarchitecture per AMD M-SPACE modular design mothodology for future microprocessors. Bulldozer will be designed for processors in the 10 W to 100 W category, implementing SSE5 and can be combined with GPU cores (Fusion).
Bobcat processor core - Bobcat is the counterpart to Bulldozer in the 1 W to 10 W power category, the microprocessor core is in fact a very simplfied x86 core. As with Bulldozer, Bobcat will also be able to be combined with GPUs under the Fusion project.