Layout Versus Schematic

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The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.

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[edit] Background

A successful Design rule check (DRC) ensures that the layout conforms to the rules designed/required for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. This is where an LVS check is used.

[edit] LVS Check

LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. The software then compares them with the schematic or circuit diagram.

LVS Checking involves following three steps:

  1. Extraction: The software program takes a database file containing all the layers drawn to represent the circuit during layout. It then runs the database through many logic operations to determine the semiconductor components represented in the drawing by their layers of construction. It then examines the various drawn metal layers and finds how each of these components connects to others.
  2. Reduction: During reduction the software combines the extracted components into series and parallel combinations if possible and generates a netlist representation of the layout database.
  3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic. If the two netlists match, then the circuit passes the LVS check. At this point it is said to be "LVS clean."

In most cases the layout will not pass LVS the first time requiring the layout engineer to examine the LVS software's reports and make changes to the layout. Typical errors encountered during LVS include:

  1. Shorts: Two or more wires that should not be connected together have been and must be separated.
  2. Opens: Wires or components that should be connected are left dangling or only partially connected. These must be connected properly to fix this.
  3. Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt MOS device instead of a standard Vt MOS device)
  4. Missing Components: An expected component has been left out of the layout.
  5. Property Errors: A component is the wrong size compared to the schematic.

[edit] LVS Software

[edit] Commercial LVS Software

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