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Contents

Intel reveals a 90 -nanometer Logic Process

Semiconductor juggernaut,

Intel reveals a 90 -nanometer logic process. The 90 nanometer ( 90 nm) logic process features cutting edge technology such as strained silicon , high-speed copper interconnects and a new low-k dielectric material. The copper interconnects alone unleashes an amazing 18% in reduced capacitance compared to silicon based ( SiOf ) dielectrics used on 0.13 um process, the previous generation just before the 90 nm .

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Intel is utilizing this build record breaking silicon structures and 
     plans to implement this process next year (2003) using 300 mm wafers. 
     Intel has been a genuine paradigm of Moore's Law for a decade by unveiling
a new forefront process generation every two years.		 <IMG 
     title="The smallest ever to be designed into a commercial microprocessor. Hundreds of these could fit inside a red blood cell. " 
     height=130 alt="Intel's 90 nm transistor" 
     src="Intel's 90 nm Process.files/90nm2.jpe" width=160 border=1> 
The smallest ever to be designed into a commercial 
     microprocessor. Hundreds of these could fit inside a red blood cell.

[Ramifications]

The 90 nm process will enable construction of 50 nm

gate-length transistors. This would be come the industry's smallest. The most advanced transistors, which are found in the Pentium 4 measure 60nm. Transitors are the building blocks of for CPUs. The 90 nm process are also currently used to construct an astounding 120 billion 52 Mbit SRAM chips in only one 300 mm wafer.

Intel expects to further improve gate lengths as it readies the process technology for volume manufacturing. Shrinking the gate size increases the drive current and lowers the parasitic capacitance of the transistor, enabling faster switching speeds. Intel declined to specify its transistor device speed.

[Cutting-edge technology]

[Strained silicon]

Strained silicon is a technique where a layer of

silicon germanium is deposited on top of a silicon substrate. The atoms in the silicon substrate naturally seek to align themselves with the atoms in the germanium above, stretching the silicon. This allows electrons to flow more smoothly between the two substances, which increases processor speed without having to make any changes to the size of the transistors. Strained silicon removes obstructions in the path of electron flow enhancing speed. Specifically an increase of as much as 10-20% in transistor current flow ( drive current) . The enhancement in performance manifests both in the NMOS and PMOS transistor. No shorting or junction leakage occurs. The related processing costs increases by only a 2 %. Strained silicon is a pioneering technology unique in the industry only to to Intel.

<A name=interconnect>[90 nm Generation Interconnects ]</A>

The

dielectric is a carbon-doped oxide ( CDO) , known as 'Low-K', and reduces capacitances by 18% compared to SiOF dielectrics of the previous 0.13 um generation. Reduced capacitance increase intra-chip communications speeds and reduces chip power. A simple dual layer also lowers capacitance and costs. The interconnect is copper and composed of 7 layers which is one more than the 0.13 um generation. The extra layer lowers costs in terms of logic density.

<A name=applications>[Record breaking applications ]</A>

Intel achieved

the world's highest capacity SRAM chips at 52 megabits using its 90 nm process in February. These chips also achieves a first in the industry in SRAM cell size of one square micron which is highly coveted by silicon manufacturers. </BODY></HTML>