Talk:Joint Test Action Group

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Hi all, nice job on the page so far. Especially given much of the history is lacking on the web. Just tried to add a little bit of history. Note that the security vulnerability section is a blatant advertisement. All those links and mention should likely be taken out or limited to one sentence. I will try to find more documents and links to history to help your page out. Feel free to accept or modify anything I put in. BTW, I did not work for Intel. In fact, we were the ones who forced Intel into adding JTAG (NCR/Teradata Mainframe group) in 1990. We built a 1024 processor supercomputer that year that had every IC and board on a JTAG scan system. We could hot plug any board and test any internal chip or register while the system was online. We even built PSR and CRC checks into a special JTAG control chip that was placed on each board. Even the back plane was scannable! SurplusGadgets 19:17, 22 May 2007 (UTC) SurplusGadgets (aka randyh@sevni.com)

i know i'm nitpicking a bit, but "enables a programmer to access an on-chip debug module which is integrated into the CPU via JTAG" in the first paragraph is ambiguous (to me). Does the programmer access the debug module via JTAG or is the debug module integrated into the CPU using JTAG? I would suspect the former, but it's not clear.
>the Dbeugmodul is realized in the CPU with a JTAG Interface :) Some Debug Interfaces are only under NDA.

Warning:
The Etoolssmiths Guardian Jtag Tools :
http://www.etoolsmiths.com/guardian.html
The following Information , I get:
Effective immediately, Embedded Toolsmiths(ETC) will no longer sell the Guardian-SE/Agile-DB emulator/debugger products.

ETC will honor support of the products for at least one year from purchase. Support inquiries can be directed to support@etoolsmiths.com.


Question: Would it make sense to publish the IEEE 1149.1 State Machine or might this be a problem, because of copyright issues ? —Preceding unsigned comment added by 84.154.55.78 (talk) 12:34, 4 November 2007 (UTC)

[edit] Picture(s)

Can somebody take a pictures of a JTAG cable, connector, and/or port to add to this? Also, would an eye pattern be useful here? --W0lfie (talk) 14:59, 21 December 2007 (UTC)


 It is requested that a photograph or photographs be included in this article to improve its quality.
The Free Image Search Tool (FIST) may be able to locate suitable images on Flickr and other web sites.

[edit] JTAG pinouts

I think this paragraph is quite wrong, I would recommend complete re-write (I can do it and supply also a photo as per previous request):

There are only minimal standards for JTAG adapters, even when standard 2.54mm pin spacing is used. For example, ARM based systems often use a 20-pin header; but many systems from TI use a 14-pin header which includes one interface for an ARM core and second one for a DSP core. Atmel's AVR 8-bit and 32-bit processors use a 10-pin JTAG header. Some systems use 12-pin headers, others use 6-pin single-row header. Higher end products frequently use dense connectors to support high-speed tracing in conjunction with JTAG operations. A recent trend is to have development boards integrate a USB interface to JTAG. Production boards often rely on bed-of-nails connections for testing and programming.


  • "recent trend having USB to JTAG..." is IMHO not 100% true, although some boards DO have USB-JTAG on itself
  • There are only few commonly used JTAG pinouts:
  1. for PLD programming, 8 or 9 pin in one row
  2. Altera ByteBlaster/AVR/... and compatible 2x5 pin
  3. ARM 14pin and 20pin JTAG
  4. MIPS EJTAG

The above pinouts are common for multiple products and vendors (i.e. almost all ARM chips use 20 or 14 pin JTAG with same pinout).

81.201.62.154 (talk) 15:07, 2 June 2008 (UTC) (no wiki account)