Flash ADC
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A Flash ADC (also known as a Direct conversion ADC) is a type of analog-to-digital converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to compare the input voltage to successive reference voltages. Often these reference ladders are constructed of many resistors; however modern implementations show that also capacitive voltage division is possible. The output of these comparators is generally fed into a digital encoder which converts the inputs into a binary value (the collected outputs from the comparators can be thought of as a unary value).
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[edit] Benefits and drawbacks
Flash converters are extremely fast compared to many other types of ADCs which usually narrow in on the "correct" answer over a series of stages. Compared to these, a Flash converter is also quite simple and, apart from the analog comparators, only requires logic for the final conversion to binary.
A Flash converter requires a huge number of comparators compared to other ADCs, especially as the precision increases. A Flash converter requires 
comparators for an n-bit conversion. The size and cost of all those comparators makes Flash converters generally impractical for precisions much greater than 8 bits (255 comparators). In place of these comparators, most other ADCs substitute more complex logic which can be scaled more easily for increased precision.
[edit] Implementation
Flash ADCs have been implemented in many technologies, varying from silicon based bipolar (BJT) and complementary metal oxide FETs (CMOS) technologies till rarely used III-V technologies. Often this type of ADCs is used as a first medium sized analog circuit verification.
The earliest implementations consisted of a reference ladder of well matched resistors connected to a reference voltage. Each tap at the resistor ladder is used for one comparator, possibly preceded by an amplification stage, and thus generates a logical '0' or '1' depending if the measured voltage is above or below the reference voltage of the resistor tap. The reason to add an amplifier is twofold: it amplifies the voltage difference and therefore suppresses the offset of the comparator and the kick-back noise of the comparator, towards the reference ladder, is also strongly suppressed. Typically designs from 4-bit up to 6-bit, and sometimes 7-bit are produced.
To save some power, designs with a capacitive reference ladders have been demonstrated. Instead of only clocking the comparator(s), also the input stage is sampling its reference value. As the sampling is done at a very high rate, the leakage of the capacitors is negligible.
Recently, offset calibration has been introduced in the flash ADC designs. Instead of properly designing the analog circuit (which actually means increasing the components sizes to suppress variation) the offset is removed during use. A test signal is applied and each the offset of each comparator is calibrated to below the LSB size of the ADC. Due to the heavy calibration effort the design are up to now always limited to 4-bits.
[edit] Folding ADC
The number of comparators can be reduced somewhat by adding a folding circuit in front, making a so called "folding ADC". Instead of using the comparators in a Flash ADC only once, during a ramp input signal, the folding ADC re-uses the comparators multiple times. If a 
-times folding circuit is used in an n-bit ADC, the actual number of comparator can be reduced from to 
(there is always one needed to detect the range crossover). Typical folding circuits are e.g. the Gilbert multiplier, or analog wired-OR circuits.
[edit] Application
The very high sample rate of this type of ADC enable Gigahertz applications like radar detection, wide band radio receivers and optical communication links. More often the flash ADC is embedded in a large IC containing many digital decoding functions. Also a small flash ADC circuit may be present inside a Delta-sigma modulation loop.
[edit] See also
[edit] References
- Analog to Digital Conversion
- Understanding Flash ADCs
- "Integrated Analog-to-Digital and Digital-to-Analog Converters ", R. van de Plassche, ADCs, Kluwer Academic Publishers, 1994.
- "A Precise Four-Quadrant Multiplier with Subnanosecond Response", Barrie Gilbert, IEEE Journal of Solid-State Circuits, Vol. 3, No. 4 (1968), pp. 365-373
