Engineering Change Order

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Engineering Change Order (ECO) is used for changes in documents such as processes and work instructions. It may also be used for changes in specifications.

ECOs are also called an Engineering Change Note or Engineering Change Notice(ECN) or just engineering change (EC).

In a typical system development cycle, the specification or the implementation is likely to change during engineering development or during integration of the system elements. These last-minute design changes are commonly referred to as engineering change orders (ECOs) and affect the functionality of a design after it has been wholly or partially completed. ECOs can compensate for design errors found during debug or changes that are made to the design specification to compensate for design problems in other areas of the system design.

In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, place, route, layout extraction, and timing verification. Electronic Design Automation tools are often built with incremental modes of operation to facilitate this type of ECO.

After masks have been made, ECOs may be done to save money. If a change can be implemented by modifying only a few of the layers (typically metal) then the cost is much less than it would be if the design was re-built from scratch. This is because starting the process from the beginning will almost always require new photomasks for all layers, and each of the 20 or so masks in a modern semiconductor fabrication process is quite expensive. A change implemented by modifying only a few layers is typically called a metal-mask ECO. Designers often sprinkle a design with unused logic gates, and EDA tools have specialized commands, in order to make this process easier.

One of the most common ECOs in ASIC design is the Gate-level netlist ECO. In this flow, engineers manually (and often tediously) hand-edit the gate level netlist, instead of re-running logic synthesis. The netlist files have to be searched for the logic affected by the change, the files need to be edited to implement the changes up and down the hierarchy, and the changes need to be tracked and verified to make sure exactly what needs to change gets changed and nothing more. This is a very time and resource intensive process that is easily subject to errors. Therefore formal equivalence checking is normally used after ECOs to ensure the revised implementation matches the revised specification.