Dual in-line package

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A Motorola 68451 MMU in a 64-pin CERDIP

ICs in DIP14-Package

In microelectronics, a dual in-line package (DIP), sometimes called a DIL package, is an electronic device package with a rectangular housing and two parallel rows of electrical connecting pins, usually protruding from the larger sides of the package and bent downward. A DIP is usually referred to as a DIPn, where n is the total number of pins. For example, a microcircuit package with two rows of seven vertical leads would be a DIP14.

DIPs may be used for integrated circuits (ICs, "chips"), like microprocessors, or for arrays of discrete components such as resistors or toggle switches. They can be mounted on a printed circuit board (PCB) either directly using through-hole technology, or using inexpensive sockets to allow for easy replacement of the device and to reduce the risk of overheat damage during soldering.

Dual in-line packages were invented at Fairchild in 1965 and, by allowing integrated circuits to be packaged more densely than previous round packages, made it possible to build complex systems such as computers. ^[1] The package was well-suited to automated assembly equipment; a printed circuit board could be populated with scores or hundreds of ICs, then have all devices soldered at once and passed on to automated testing machine, with very little human labor required. However, the packages were still large with respect to the integrated circuits within them. By the end of the 20th century, most ICs were packaged in surface-mount packages, which allowed further reduction in the size of systems.

DIPs were the mainstream of the microelectronics industry in the 1970s and 80s. Their use has subsided in recent years due to the emerging new surface-mount technology (SMT) packages such as PLCC and SOIC.

For programmable devices like EPROMs and GALs, DIPs remained popular for many years due to their easy handling with external programming circuitry. However, with In-System Programming (ISP) technology now state of the art, this advantage of DIPs is rapidly losing importance as well. Through the 1990s, devices with pin counts below 20 were manufactured in a DIP format in addition to the newer formats. Since about 2000, newer devices are often unavailable in the DIP format.

1 Pin spacing
2 Orientation and pin numbering
3 See also
4 References
5 External links

[edit] Pin spacing

Several PDIPs and CERDIPS. The large CERDIP in the foreground is an 8080 processor.

Sockets for 16-, 14-, and 8-pin packages.

The most common DIPs have an inter-lead spacing (lead pitch) of 0.1" (2.54 mm) and a row spacing of either 0.3 in (7.62 mm) or 0.6 in (15.24 mm). Typical pin counts are 8 or any even number from 14 to 24 (less common 28) for 0.3 in packages, and 24, 28, 32 or 40 (less common 36, 48 or 52) for 0.6 in packages. Where there is a need to differentiate between the two widths for the same pin count the term "Skinny DIP" is used to refer to the 0.3 in version. JEDEC-standards also specify less common packages with a row spacing of 0.4 in (10.16 mm), or 0.9 in (22.86 mm) with a pin-count of up to 64. Other standardized variants include a lead pitch of 0.07 in (1.778 mm) at a row spacing of 0.3 in, 0.6 in or 0.75 in. The former Soviet Union and Eastern bloc countries used similar packages, but with a metric inter-lead spacing of 2.5 mm, rather than 2.54 mm (or 0.1 in).

Several DIP variants exist, mostly distinguished by packaging material:

Ceramic Dual In-line Package (CERDIP)
Plastic Dual In-line Package (PDIP)
Shrink Plastic Dual In-line Package (SPDIP) – A shrink version of the PDIP with a 0.07 in (1.778 mm) lead pitch

NE555 from Signetics in an 8-pin DIP

[edit] Orientation and pin numbering

Pin numbering is counter-clockwise.

DIPs have an orientation notch or dot on one end. If the chip is held so that the long axis is vertical and the notch is at the top end, pin #1 is the topmost pin in the left column. Pins are numbered counter-clockwise from there, i.e. top to bottom along the left column, then bottom to top along the right column. This allows automated chip-insertion machinery to ensure correct orientation of the chip by mechanical sensing.