Double data rate

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In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition.

The simplest way to design a clocked electronic circuit is to make it perform one transfer per full cycle (rise and fall) of a clock signal. This, however, requires that the clock signal operate twice as fast as the data signals, which change at most once per transfer. When operating at high speed, signal integrity limitations constrain the clock frequency. By using both edges of the clock, the data signals operate at the same limiting frequency, doubling the data transmission rate.

This technique has been used for microprocessor front side busses, Ultra-3 SCSI, the AGP bus, DDR SDRAM, and the HyperTransport bus on AMD's Athlon 64 processors.

An alternative to double or quad pumping is to make the link self-clocking. This tactic was chosen by InfiniBand and PCI Express.

Describing the speed of a double-pumped bus can be confusing. Each clock edge is referred to as a "beat", with two beats (one upbeat and one downbeat) per cycle. Some people talk about the basic clock frequency, while others refer to the number of transfers per second. Careful usage generally talks about "500 MHz, double data rate" or "1000 MT/s", but people will refer casually to a "1000 MHz bus", even though no signal cycles faster than 500 MHz.

DDR SDRAM popularized the technique of referring to the bus bandwidth in megabytes per second, the product of the transfer rate and the bus width in bytes. DDR SDRAM operating with a 100 MHz clock is called DDR-200 (after its 200 MT/s data transfer rate), and a 64 bit (8 byte) wide DIMM operated at that speed is called PC-1600, after its 1600 MB/s peak (theoretical) bandwidth.

Note that DDR SDRAM only uses double-data-rate signalling on the data lines. Address and control signals are still sent to the DRAM once per clock cycle.