Don't-care

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In logic synthesis and logic simulation a don't care or X value is one value in a multi-valued logic system that denotes an unknown value, or a value that the designer (for whatever reason) does not care about. In the Verilog hardware description language such values are denoted by the letter "X". In the VHDL hardware description language such values are denoted (in the standard logic package) by the letter "X" (forced unknown) or the letter "W" (weak unknown).^[1]

An X value does not exist in hardware. In simulation, an X value can result from two or more sources driving a signal simultaneously, or the stable output of a flip-flop (electronics) not having been reached. In synthesized hardware, however, the actual value of such a signal will be either 0 or 1, but will not be determinable from the circuit's inputs.^[1]

Synthesis tools can use don't care values to determine where and how to perform area optimization. A synthesis tool can use don't care values to reduce the circuit sizes of finite state machines, for example.^[1]

[edit] See also

• Karnaugh map

[edit] References

1. ^ ^{a b c} David Naylor and Simon Jones (1997). Vhdl: A Logic Synthesis Approach. Springer, 14–15,219,221. ISBN 0412616505.