DIMM

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Two types of DIMMs: a 168-pin SDRAM module (top) and a 184-pin DDR SDRAM module (bottom).

A DIMM, or dual in-line memory module, comprises a series of dynamic random access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers. DIMMs began to replace SIMMs (single in-line memory modules) as the predominant type of memory module as Intel's Pentium processors began to gain market share.

The main difference between SIMMs and DIMMs is that DIMMs have separate electrical contacts on each side of the module, while the contacts on SIMMs on both sides are redundant. Another difference is that standard SIMMs have a 32-bit data path, while standard DIMMs have a 64-bit data path. Since Intel's Pentium has (as do several other processors) a 64-bit bus width, it required SIMMs installed in matched pairs in order to complete the data bus. The processor would then access the two SIMMs simultaneously. DIMMs were introduced to eliminate this practice.

The most common types of DIMMs are:

72-pin SO-DIMM (not the same as a 72-pin SIMM), used for FPM DRAM and EDO DRAM
100-pin DIMM, used for printer SDRAM
144-pin SO-DIMM, used for SDR SDRAM
168-pin DIMM, used for SDR SDRAM (less frequently for FPM/EDO DRAM in workstations/servers)
172-pin MicroDIMM, used for DDR SDRAM
184-pin DIMM, used for DDR SDRAM
200-pin SO-DIMM, used for DDR SDRAM and DDR2 SDRAM
214-pin MicroDIMM, used for DDR2 SDRAM
240-pin DIMM, used for DDR2 SDRAM, DDR3 SDRAM and FB-DIMM DRAM

There are 2 notches on the bottom edge of 168-pin-DIMMs, and the location of each notch determines a particular feature of the module.

The first notch is DRAM key position. It represents RFU (reserved future use), registered, and unbuffered.
The second notch is voltage key position. It represents 5.0V, 3.3V, and Reserved.
The upper DIMM in the photo is an unbuffered 3.3V 168-pin DIMM.

A DIMM's capacity and timing parameters may be identified with SPD (Serial Presence Detect), an additional chip which contains information about the module type.

ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect (SECDED) which uses a 9th extra bit per byte.

1 Ranking
2 Organization
3 Speeds
4 Form factors
5 See also
6 External links

[edit] Ranking

The number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM ie 64 bits. The ranks cannot be accessed simultaneously as they share the same datapath. The physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks. Sometimes the layout of all DRAM on one side of the DIMM PCB versus both sides is referred to as "single-sided" versus "double-sided". These terms may cause confusion as they do not necessarily relate to how the DIMMs are logically organized or accessed.

For example, on a single rank DIMM that has 64 data bits of I/O pins, there is only one set of DRAMs that are turned on to drive a read or receive a write on all 64-bits. In most electronic systems, memory controllers are designed to access the full data bus width of the memory module at the same time.

On a 64-bit (non-ECC) DIMM made with two ranks, there would be two sets of DRAM that could be accessed at different times. Only one of the ranks can be accessed at a time, since the DRAM data bits are tied together for two loads on the DIMM (Wired OR). Ranks are accessed through chip selects (CS). Thus for a two rank module, the two DRAMs with data bits tied together may be accessed by a CS per DRAM (e.g. CS0 goes to one DRAM chip and CS1 goes to the other). DIMMs are currently being commonly manufactured with up to four ranks per module.

Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs. JEDEC decided that the terms "dual-sided," "double-sided," or "dual-banked" were not correct when applied to registered DIMMs.

[edit] Organization

Most DIMMs are built using "x4" (by 4) memory chips or "x8" (by 8) memory chips. "x4" or "x8" refer to the data width of the DRAM chips in bits.

In the case of the "x4" Registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked.

For "x8" Registered DIMMs, each side is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked).

[edit] Speeds

For various technologies, there are certain bus and device clock frequencies that are standardized. There is also a decided nomenclature for each of these speeds for each type.

SDRAM DIMMs - These first synchronous registered DRAM DIMMs had the same bus frequency for data, address and control lines.

PC66 = 66 MHz
PC100 = 100 MHz
PC133 = 133 MHz

DDR SDRAM (DDR1) SDRAM DIMMs - DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes.

PC1600 = 200 MHz data & strobe / 100 MHz clock for address and control
PC2100 = 266 MHz data & strobe / 133 MHz clock for address and control
PC2700 = 333 MHz data & strobe / 166 MHz clock for address and control
PC3200 = 400 MHz data & strobe / 200 MHz clock for address and control

DDR2 SDRAM SDRAM DIMMs - DIMMs based on Double Data Rate 2 (DDR2) DRAM also have data and data strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR2 is significantly lower than DDR(1) at the same speed.

PC2-3200 = 400 MHz data & strobe / 200 MHz clock for address and control
PC2-4200 = 533 MHz data & strobe / 266 MHz clock for address and control
PC2-5300 = 667 MHz data & strobe / 333 MHz clock for address and control
PC2-6400 = 800 MHz data & strobe / 400 MHz clock for address and control
PC2-8000 = 1000 MHz data & strobe / 500 MHz clock for address and control
PC2-8500 = 1066 MHz data & strobe / 533 MHz clock for address and control

DDR3 SDRAM SDRAM DIMMs - DIMMs based on Double Data Rate 3(DDR3) DRAM have data and strobe frequencies at double the rate of the clock. This is achieved by clocking on both the rising and falling edge of the data strobes. The power consumption and voltage of DDR3 is lower than DDR2 of the same speed.

PC3-6400 = 800 MHz data & strobe / 400 MHz clock for address and control
PC3-8500 = 1066 MHz data & strobe / 533 MHz clock for address and control
PC3-10600 = 1333 MHz data & strobe / 667 MHz clock for address and control
PC3-12800 = 1600 MHz data & strobe / 800 MHz clock for address and control

[edit] Form factors

Several form factors are commonly used in DIMMs. Single Data Rate (SDR) SDRAM DIMMs commonly came in two main sizes: 1.7" and 1.5". When 1U rackmount servers started becoming popular, these form factor Registered DIMMs had to plug into angled DIMM sockets to fit in the 1.75" high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "Low Profile" (LP) height of ~1.2". These fit into vertical DIMM sockets for a 1U platform. With the advent of blade servers, the LP form factor DIMMs have once again been often angled to fit in these space constrained boxes. This led to the development of the Very Low Profile (VLP) form factor DIMM with a height of ~.72" (18.3 mm). Other DIMM form factors include the SO-DIMM, the Mini-DIMM and the VLP Mini-DIMM.