Cyrix III

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Cyrix III
Central processing unit

Produced: From February 2000 to Early 2001
Manufacturer: Cyrix
Max CPU clock: 350 MHz to 800 MHz
FSB speeds: 100 MHz to 133 MHz
Min feature size: 0.18 µm to 0.15 µm
Instruction set: x86
Socket: Socket 370
Core names:
  • Joshua
  • Samuel (C5A)
  • Samuel 2 (C5B)

Cyrix III is an x86-compatible Socket 370 CPU. VIA Technologies launched the processor in February 2000. VIA had recently purchased both Centaur Technology and Cyrix. Cyrix III was to be based upon a core from one of the two companies.

Contents

[edit] CPU cores

[edit] Joshua

The pre-release Cyrix III CPUs were based upon a 22 million transistor Joshua core designed by Cyrix.[1] This CPU core was a typical Cyrix CISC design with a very high IPC rate but rather low clock rates. To compensate this, Cyrix used a rating system with a higher "P-Rating" than the true clock rate to emphasize the higher performance of their designs compared to the competitors' offerings. This was controversial, however, because the PR ratings did not account for the very low floating point performance of the processor.[2] When the chip reached reviewers, the CPU's performance was discovered to be low compared to the competition. And to intensify the negative attention, there were stability problems with the processor.[citation needed]

[edit] Samuel

Because the Joshua core was such a mixed result in thermal output, core size, and performance, VIA switched almost immediately to an 11 million transistor Samuel core designed by Centaur Technology.[3] The Samuel core was a simpler RISC design, being an evolution of the WinChip processors (the unreleased WinChip 4). Samuel was designed for higher clock speeds, with more L1 cache (but no L2), and used smaller manufacturing technology.[4] While this version of Cyrix III still had sub-par performance compared to the competition from Intel and AMD, it was quite power efficient and consisted of only half the number of transistors of Cyrix's creation.[4][5]

VIA dropped the criticized PR rating with new processors based on the Samuel core, in favor of simply distinguishing them by their actual clock speed.

[edit] Samuel 2

The Samuel 2 core is a revision to the Samuel core. The Centaur Technology team added an on-die 64 KiB L2 cache and moved to a 150 nm manufacturing process. These changes improved per-clock performance, reduced power demands, and increased clock speed scalability.[5]

[edit] Renamed

The VIA Cyrix III was later renamed VIA C3, as it was not built upon Cyrix technology at all.

[edit] See also

[edit] References

  1. ^ VIA Cyrix III, CPU Scorecard, October 8, 2005.
  2. ^ Loki.Joshua, Ars Technica, accessed May 11, 2007.
  3. ^ Witheiler, Matthew. [1] The New VIA Cyrix III: The Worlds First 0.15 Micron x86 CPU], Anandtech, January 5, 2001.
  4. ^ a b De Gelas, Johan. Cyrix III, An Alternative Approach, Ace's Hardware, August 6, 2000.
  5. ^ a b Poluvyalov, Alexander. VIA Cyrix III (Samuel 2) 600 and 667 MHz, Digit Life, accessed May 12, 2007.

[edit] External links

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