Configware
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Configware (Configuration Ware) is the program source for morphware, i. e. for reconfigurable platforms like FPGAs (field-programmable gate arrays), or, to coarse- grained reconfigurable platforms like reconfigurable datapath arrays (rDPAs). Software is the counterpart to configware. In contrast to software which is instruction-stream-based and deserves procedural programming for instruction scheduling onto von-Neumann-like machine resources, configware deserves structural programming like e. g. for placement and routing before the application run time.
As configware code, configware also refers to the bit code configuration files for a FPGA (field-programmable gate array), or, for a rDPA (Morphware). These files specify the configuration of logic blocks internal to the device, and the interconnection between blocks, and external I/O. Configware code files are unique to a particular manufacturer's part. They may be handled with software-like configuration management procedures. When configuration is completed so that the resources are ready for use, suitable Flowware has to be compiled for data scheduling.
To-day, configware compilers and other configware application development support tools are usually implemented as software running on von-Neumann-like processors. This may change in the future. In contrast to operating systems for software (SW-OS), emerging operating systems for configware (CW-OS) deserve to manage multi-tasking and other administrative jobs on reconfigurable platforms.
The CW-OS is especially important for dynamically reconfigurable systems, where parts of the reconfigurable resources are at execution mode when, at the same time, other parts are at configuration mode, and also, where in addition to this a swapping of configware code modules helps flexibility and to save resources. Prof. Reiner Hartenstein, TU Kaiserslautern, has coined term "Configware" the mid 90's.
[edit] Compiler
A Configware Compiler is used in the area of Reconfigurable Computing for data-stream-based reconfigurable systems using platforms like FPGAs or coarse-grained reconfigurable datapath arrays (rDPAs) to generate two different blocks of code: configware code and flowware code (see figure). By placement and routing the mapper generates the configware code for reconfiguration of the platform. Based on the mapper's result the data scheduler generates the flowware code which is used to organize the data streams needed by programming the data counters through reconfiguration of the address generators, such as for instance Generic address generators GAG, in the Auto-sequencing memory (ASM) blocks. A configware compiler may be, for instance, part of a Configware/Software Co-Compiler.
The fundamental architectural model behind this methodology is the Super systolic array (KressArray), a generalization of the systolic array having been derived by Rainer Kress, who replaced the algebraic synthesis models known from original systolic arrays restricting their use only to applications with regular data dependencies, by simulated annealing merging both the mapper and the data scheduler.
