Circuit complexity

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Circuit complexity is a topic in computational complexity theory, a branch of theoretical computer science which classifies boolean functions according to the amount of computational resources needed to compute them. In circuit complexity, these resources are size and depth of boolean circuits.

A boolean circuit with n input bits is a directed acyclic graph in which every node (usually called gates in this context) is either an input node of in-degree 0 labeled by one of the n input bits, an AND gate, an OR or a NOT gate. One of these gates is designated as the output gate. Such a circuit naturally computes a function of its n inputs. The size of a circuit is the number of gates it contains and its depth is the maximal length of a path from an input gate to the output gate.

The circuit-size (respectively circuit-depth) complexity of a boolean function f is the minimal size (respectively minimal depth) of any circuit computing f. The goal of circuit complexity is to determine this optimal size/depth for natural families of boolean functions. Most often the challenge involves the study of the asymptotic behavior of size or depth complexity for sequences of boolean functions $f 1, f 2,...$ where each $f n$ is a function of n bits.

Complexity classes defined in terms of boolean circuits include AC⁰, AC, TC⁰ and NC.

1 Uniformity
2 History
- 2.1 Key results
3 Complexity classes
4 References

[edit] Uniformity

Boolean circuits are one of the prime examples of so-called non-uniform models of computation in the sense that inputs of different lengths are processed by different circuits, in contrast with uniform models such as Turing machines where the same computational device is used for all possible input lengths. An individual computational problem is thus associated with a particular family of boolean circuits $C 1, C 2,...$ where each $C n$ is the circuit handling inputs of n bits. A uniformity condition is often imposed on these families so that each individual circuit can be computed by some resource-bounded Turing machine.

[edit] History

In his 1999 book on circuit complexity, Vollmer states (pg. 1) that "the direction which complexity theoretic research on circuits took was heavily influenced by Savage's textbook", citing Savage 1976.

[edit] Key results

The boolean function PARITY, which is 1 if and only if the sum of its input bits is odd, does not lie in $A C 0$ . The result was first established independently by Ajtai (1983) and by Furst, Saxe and Sipser (1984). Later improvements by Hastad (1987) in fact establish that any family of $A C 0$ computing PARITY requires exponential size. Smolensky (1986) proved that this is true even if the circuit is augmented with gates computing the sum of its input bits modulo some odd prime p.
Consider the clique problem of determining whether a graph with n vertices has a clique of size k. For any particular choice of n and k this can be encoded as a boolean function on n(n−1) inputs, one for each pair of vertices, specifying whether or not that edge is in the graph. This family of functions is monotone and can be computed by a family of circuits, but it has been shown that it cannot be computed by a polynomial-size family of monotone circuits (that is, circuits with AND and OR gates but no negation). This original result of Razborov (1985) was later improved to an exponential-size lower bound by Alon and Boppana (1987). Raz and McKenzie later showed that the monotone NC hierarchy is infinite (1999).
Division lies in uniform TC0 (Hesse 2001).

[edit] Complexity classes

Many circuit complexity classes are defined in terms of class hierarchies. For each integer i, there is a class NCⁱ, consisting of polynomial-size circuits of depth $O (log i (n))$ , using bounded fan-in AND, OR, and NOT gates. We can talk about the union NC of all of these classes. By considering unbounded fan-in gates, we construct the classes ACⁱ and AC. We construct many other circuit complexity classes with the same size and depth restrictions by allowing different sets of gates.