Capacitance voltage profiling
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The "CV", or more correctly "C-V", in C-V profiling, stands for capacitance-voltage, and refers to a technique used for characterization of semiconductor materials and devices. The technique uses a metal-semiconductor junction (Schottky barrier) or a p-n junction [1] or a MOSFET to create a depletion region, a region which is empty of conducting electrons and holes, but may contain ionized donors and electrically active defects or traps. The depletion region with its ionized charges inside behaves like a capacitor. By varying the voltage applied to the junction it is possible to vary the depletion width. The dependence of the depletion width upon the applied voltage provides information on the semiconductor's internal characteristics, such as its doping profile and electrically active defect densities.[2], [3] Measurements may be done at DC, or using both DC and a small-signal AC signal (the conductance method [3], [4]), or using a large-signal transient voltage.[5]
[edit] See also
- Depletion region
- Metal–oxide–semiconductor structure
- Depletion width
- Deep-level transient spectroscopy
[edit] References and notes
- ^ J. Hilibrand and R.D. Gold, "Determination of the Impurity Distribution in Junction Diodes From Capacitance-Voltage Measurements", RCA Review, vol. 21, p. 245, June 1960
- ^ Alain C. Diebold (Editor) (2001). Handbook of Silicon Semiconductor Metrology. CRC Press, p. 59-60. ISBN 0824705068.
- ^ a b J.R. Brews and E.H. Nicollian (2002). MOS (Metal Oxide Semiconductor) Physics and Technology. Wiley. ISBN 047143079X.
- ^ Andrzej Jakubowski, Henryk M. Przewłocki (1991). Diagnostic Measurements in LSI/VLSI Integrated Circuits Production. World Scientific, p. 159. ISBN 9810202822.
- ^ Sheng S. Li and Sorin Cristoloveanu (1995). Electrical Characterization of Silicon-On-Insulator Materials and Devices. Springer, Chapter 6, p. 163. ISBN 0792395484.