C-element

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The Muller C-element, or Muller C-gate, is a commonly used asynchronous logic component originally designed by David E. Muller. It applies logical operations on the inputs and has hysteresis. The output of the C-element reflects the inputs when the states of all inputs match. The output then remains in this state until the inputs all transition to the other state. This model can be extended to the Asymmetric C-element where some inputs only effect the operation in one of the transitions (positive or negative). The figure shows the gate-level and transistor-level implementations and symbol of the C-element.

To understand how this works, look at the transistor-level implementation more closely:

The C-element stores its previous state with two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks.

If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either V_dd or ground, and so the weak inverter (drawn smaller in the diagram) dominates and the latch outputs its previous state.

The Muller C-element was first used in the arithmetic logic unit (ALU) of the ILLIAC II supercomputer, proposed in 1958, and operational in 1962.

[edit] Truth Table

Here is the truth table for a 2-input c-gate. Y_{n − 1} denotes a "no change" condition.

A B	Y
0 0	0
0 1	Yn − 1
1 0	Yn − 1
1 1	1

[edit] External links

• Muller C-Gate Simulation