Bus sniffing

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Bus sniffing or Bus snooping is a technique used in distributed shared memory systems and multiprocessors aimed at achieving cache coherence. Every cache controller monitors the bus, awaiting for broadcasts which may cause it to invalidate its cache line.

Cache line most commonly is in states "dirty", "invalid" and "valid" or "shared". On read miss, request for read is broadcast on the bus. All cache controllers are monitoring the bus. The one having the copy in the state "dirty" changes it state to "valid" and sends the copy to requesting node. On write miss, invalidation of all cache copies is performed. When writing a block in state "valid", its state is changed to "dirty" and a broadcast is sent out to all cache controllers to invalidate their copies.

Since snooping does not scale well, larger ccNuma systems tend to use Directory-based coherence protocols.

[edit] Implementation

The cache would have 3 extra bits

V: valid
D: Dirty bit, signifies that data in the cache is not the same as in memory
S: Shared

Tag  | ID | V | D | S
---------------------
1111 | 00 | 1 | 0 | 0
0000 | 01 | 0 | 0 | 0
0000 | 10 | 1 | 0 | 1
0000 | 11 | 0 | 0 | 0

...After a write of address 1111 00

Tag  | ID | V | D | S
---------------------
1111 | 00 | 1 | 1 | 0
0000 | 01 | 0 | 0 | 0
0000 | 10 | 1 | 0 | 1
0000 | 11 | 0 | 0 | 0

The caching logic would look at the bus from time to time and see if any cached memory is requested. If the cache is dirty and shared and the bus requests that piece of memory the snooping elements will supply the value to the cache then 'notify everyone' who needs that memory that the address was updated.

When the other units are notified of the updated cache they will turn off the valid bit. Thus the original cache will be marked as exclusive ( S bit would be 0 )

When invalidating an address marked as dirty ( Ie one cache would have a dirty address and the other cache is writing ) then the cache will ignore that request. The new cache will be marked as dirty, valid and exclusive and that cache will now take responsibility for the address

[edit] External links

• Jim Plusquellic. Centralized Shared-Memory Architectures.