Atmel AVR

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The AVR is a Modified Harvard architecture 8-bit RISC single chip microcontroller (µC) which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to One-Time Programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time.

Contents 1 Brief History 2 Device Overview 2.1 Basic Families 2.2 Device Architecture 2.2.1 Data RAM 2.2.2 Program Memory (Flash) 2.2.3 Internal Data Memory 2.2.4 Internal Registers 2.2.5 EEPROM 2.3 Program Execution 2.4 Instruction Set 2.5 MCU Speed 2.6 Development 2.7 Features 3 Development Tools and Evaluation Kits 3.1 STK500 Starter Kit 3.2 AVR ISP and AVR ISP mkII 3.3 AVR Dragon (USB) 3.4 JTAG (IEEE 1149.1) 3.5 JTAGICE mkI 3.6 JTAGICE mkII 3.7 The Butterfly Demo Board 3.8 AT90USBKey 3.9 Raven Wireless Kit 3.10 Third-Party Programmers 4 Atmel AVR Usage 5 The New 32-Bit AVRs 6 Footnotes 7 External links

[edit] Brief History

It is believed the AVR basic architecture was conceived by two students at the Norwegian Institute of Technology (NTH) Alf-Egil Bogen and Vegard Wollan.^[1][2]

The original AVR MCU was developed at a local ASIC house in Trondheim Norway, where the two founders of Atmel Norway were working as students. It was known as a μRISC (Micro RISC). When the technology was sold to Atmel, the internal architecture was further developed by Alf and Vegard at Atmel Norway, a subsidiary of Atmel founded by the two architects.

The acronym AVR has been reported to stand for Advanced Virtual RISC, but it has also been rumoured to stand for the initials of the chip's designers: Alf and Vegard [RISC]. Atmel says that the name AVR is not an acronym and does not stand for anything in particular.

Note that the use of "AVR" in this article generally refers to the 8-bit RISC line of Atmel AVR Microcontrollers.

Among the first of the AVR line was the AT90S8515, which in a 40-pin DIP package has the same pinout as an 8051 microcontroller, including the external multiplexed address and data bus. The polarity of the /RESET line was opposite (8051's having an active-high RESET, while the AVR has an active-low /RESET), but other than that, the pinout was identical.

[edit] Device Overview

The AVR is a Modified Harvard architecture machine with program and data stored in separate physical memory systems that appear in different address spaces but having the ability to read data items from program memory using special instructions.

[edit] Basic Families

AVRs are generally classified into four broad groups:

• tinyAVRs
  • 1-8 kB program memory
  • 8-32-pin package
  • Limited peripheral set

• megaAVRs
  • 4-256 kB program memory
  • 28-100-pin package
  • Extended instruction set (Multiply instructions and instructions for handling larger program memories)
  • Extensive peripheral set

• XMEGA
  • 16-256 kB program memory
  • 44-100-pin package
  • Extended performance features, such as DMA, "Event System", and cryptography support.
  • Extensive peripheral set with DACs

• Application specific AVRs
  • megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, USB controller, advanced PWM, CAN etc.
  • FPSLIC (Field Programmable System Level Integrated Circuit), an AVR core on-die with an FPGA. The FPSLIC uses SRAM for the AVR program code, unlike all other AVRs. Partly due to the relative speed difference between SRAM and flash, the AVR core in the FPSLIC can run at up to 50MHz.

[edit] Device Architecture

[edit] Data RAM

Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the need for external memory (though still available on some devices).

[edit] Program Memory (Flash)

Program instructions are stored in non-volatile Flash memory. Although they are 8-bit MCUs, each instruction takes one or two 16-bit words.

The size of the program memory is occasionally indicated in the naming of the device itself (e.g., the ATmega64x line has 64 kB of Flash).

[edit] Internal Data Memory

The data address space consists of the register file, I/O registers, and SRAM. The AVRs have 32 single-byte registers and are classified as 8-bit RISC devices.

[edit] Internal Registers

In most variants of the AVR architecture, the working registers are mapped in as the first 32 memory addresses (0000₁₆-001F₁₆) followed by the 64 I/O registers (0020₁₆-005F₁₆).

Actual SRAM starts after these register sections (address 0060₁₆). (Note that the I/O register space may be larger on some more extensive devices, in which case the memory mapped I/O registers will occupy a portion of the SRAM address space.)

Even though there are separate addressing schemes and optimized opcodes for register file and I/O register access, all can still be addressed and manipulated as if they were in SRAM.

In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000₁₆-0FFF₁₆). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space which can be used optionally for mapping the internal EEPROM to the data address space (1000₁₆-1FFF₁₆). The actual SRAM is located after these ranges, starting at 2000₁₆.

[edit] EEPROM

Some AVR microcontrollers have internal Electrically Erasable Programmable Read Only Memory (EEPROM) for semi-permanent data storage (as versus FLASH for semi-permanent program storage). Like Flash memory, EEPROM can maintain its contents when electrical power is removed.

In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions which makes EEPROM access much slower than other internal RAM.

However, some devices in the SecureAVR (AT90SC) family ^[3] uses a special EEPROM mapping to the data or program memory depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space.

Since the number of writes to EEPROM is not unlimited - Atmel specifies 100,000 write cycles in their datasheets - a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if contents need to be changed.

[edit] Program Execution

Atmel's AVRs have a three stage, single level pipeline design. This means the next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among the eight-bit microcontrollers.

The AVR family of processors were designed with the efficient execution of compiled C code in mind and has several built-in pointers for the task.

[edit] Instruction Set

Main article: Atmel AVR instruction set

The AVR Instruction Set is more orthogonal than most eight-bit microcontrollers, in particular the PIC microcontrollers with which AVR competes today. However, it is not completely regular:

• Pointer registers X, Y, and Z have addressing capabilities that are different from each other.
• Register locations R0 to R15 have different addressing capabilities than register locations R16 to R31.
• I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63.
• CLR affects flags, while SER does not, even though they are complementary instructions. CLR set all bits to zero and SER sets them to one. (Note that CLR is pseudo-op for EOR R, R; and SER is short for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/stores/branches such as LDI do not.)

[edit] MCU Speed

The AVR line can normally support clock speeds from 0-16 MHz, with some devices reaching 32 MHz. Lower powered operation usually requires a reduced clock speed. All recent (TINY and MEGA, but not 90S) AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry.

Since many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.

[edit] Development

AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are sold under various names that share the same basic core but with different peripheral and memory combinations. Compatibility amongst chips is fairly good.

See external links for sites relating to AVR development.

[edit] Features

Current AVRs offer a wide range of features:

• Multifunction, Bi-directional General Purpose I/O ports with configurable, built-in pull-up resistors
• Multiple Internal Oscillators
• Internal, Self-Programmable Instruction Flash Memory up to 256 K
  • In-System Programmable using ISP, JTAG, or High Voltage methods
  • Optional Boot Code Section with Independent Lock Bits for Protection
• On chip debugging (OCD) support through JTAG or debugWIRE on most devices
  • The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on GPIOs. These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP or HVSP. By default, AVRs with JTAG come with the JTAG interface enabled.
  • debugWIRE uses the /RESET pin as a bi-directional communication channel to access on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin. debugWIRE can only be enabled using ISP or HVSP. Once enabled, it can only be disabled via the debugWIRE interface.
• Internal Data EEPROM up to 4 kB
• Internal SRAM up to 8 K
• External 64KB little endian data space on certain models, including the Mega8515 and Mega162.
  • The external data space is overlaid with the internal data space, such that the full 64KB address space does not appear on the external bus. An accesses to e.g. address 0x0100 will access internal RAM, not the external bus.
  • In certain members of the XMEGA series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16MB of data memory to be directly addressed.
  • AVR's generally do not support executing code from external memory. Some ASSP's using the AVR code do support external program memory.
• 8-Bit and 16-Bit Timers
  • PWM output (Dead time generator on some devices)
  • Input capture
• Analog Comparators
• 10 or 12-Bit A/D Converters, with multiplex of up to 16 channels
• 12-bit D/A Converters
• A variety of serial interfaces, including
  • I²C Compatible Two-Wire Interface (TWI)
  • Synchronous/Asynchronous Serial Peripherals (UART/USART) (used with RS-232, RS-485, and more)
  • Serial Peripheral Interface Bus (SPI)
  • Universal Serial Interface (USI) for Two or Three-Wire Synchronous Data Transfer
• Brownout Detection
• Watchdog Timer (WDT)
• Multiple Power-Saving Sleep Modes
• Lighting and motor control (PWM Specific) Controller models
• CAN Controller Support
• USB Controller Support
  • Proper High-speed hardware & Hub controller with embedded AVR.
  • Also freely available low-speed (HID) software emulation
• Ethernet Controller Support
• LCD Controller Support
• Low-voltage Devices Operating Down to 1.8v
• picoPower Devices
• DMA controllers and "Event System" peripheral communication.
• Fast Cryptography support for AES and DES

[edit] Development Tools and Evaluation Kits

Official Atmel AVR development tools and evaluation kits consists of a small number of starter kits and debugging tools with support for most AVR devices:

[edit] STK500 Starter Kit

The STK500 starter kit and development system features ISP and high voltage programming (HVP) for all AVR devices, either directly or through extension boards. The board is fitted with DIP sockets for all AVRs available in DIP packages.

STK500 Expansion Modules: Several expansion modules are available for the STK500 board:

• STK501 - Adds support for microcontrollers in 64-pin TQFP packages.
• STK502 - Adds support for LCD AVRs in 64-pin TQFP packages.
• STK503 - Adds support for microcontrollers in 100-pin TQFP packages.
• STK504 - Adds support for LCD AVRs in 100-pin TQFP packages.
• STK505 - Adds support for 14 and 20-pin AVRs.
• STK520 - Adds support for 14 and 20-pin microcontrollers from the AT90PWM family.
• STK524 - Adds support for the ATmega32M1/C1 32-pin CAN/LIN/Motor Control family.
• STK525 - Adds support for the AT90USB microcontrollers in 64-pin TQFP packages.
• STK526 - Adds support for the AT90USB microcontrollers in 32-pin TQFP packages

[edit] AVR ISP and AVR ISP mkII

The AVR ISP and AVR ISP mkII are inexpensive tools allowing all AVRs to be programmed via ICSP.

The AVR ISP connects to a PC via a serial port, and draws power from the target system. The AVR ISP allows using either of the "standard" ICSP pinouts, either the 10-pin or 6-pin connector. The AVR ISP has been discontinued, replaced by the AVR ISP mkII.

The AVR ISP mkII connects to a PC via USB, and draws power from USB. LED's visible through the translucent case indicate the state of target power.

[edit] AVR Dragon (USB)

The Dragon is an inexpensive tool allowing all AVRs to be programmed via JTAG, HVP or ICSP. The Dragon allows debugging of AVRs with 32KB or less of program memory, via JTAG or DebugWire. The Dragon has a small prototype area which can accommodate an 8, 28, or 40-pin AVR, including connections to power and programming pins. There is no area for any additional circuitry.

[edit] JTAG (IEEE 1149.1)

The Joint Test Action Group, In Circuit Emulator (JTAGICE) debugging tool supports on-chip debugging (OCD) of AVRs with a JTAG boundary-scan interface. The original JTAGICE is no longer in production, however it has been replaced by the JTAGICE mkII.

[edit] JTAGICE mkI

The JTAGICE mkI debugging tool supports on-chip debugging (OCD) of older AVRs with JTAG interface. Newer devices using the debugWire interface cannot be debugged.

[edit] JTAGICE mkII

The JTAGICE mkII debugging tool supports on-chip debugging (OCD) of AVRs with JTAG or debugWIRE interface. The debugWire interface enables debugging using only one pin (the Reset pin), allowing debugging of applications running on low pin-count microcontrollers.

[edit] The Butterfly Demo Board

Main article: AVR Butterfly

The very popular AVR Butterfly demonstration board is a self-contained, battery-powered computer running the Atmel AVR ATmega169V microcontroller. It was built to show-off the AVR family especially a new built-in LCD interface. The board includes the LCD screen, joystick, speaker, serial port, real time clock (RTC), flash memory chip, and both temperature and voltage sensors. Earlier versions of the AVR Butterfly also contained a photoresistor. The small board has a shirt pin on its back so it can be worn as a name badge.

The AVR Butterfly comes preloaded with software to demonstrate the capabilities of the microcontroller. Factory firmware can scroll your name, display the sensor readings, and show the time. The AVR Butterfly also has a piezo speaker that can be used to reproduce sounds and music.

The AVR Butterfly demonstrates LCD driving by running a 14-segment, six alpha-numeric character display. However, the LCD interface consumes many of the I/O pins.

The Butterfly's ATmega169 CPU is capable of speeds up to 8 MHz, however it is factory set by software to 2 MHz to preserve the button battery life. A pre-installed bootloader program allows the board to be re-programmed via a standard RS-232 serial plug with new programs that users can write with the free Atmel IDE tools.

[edit] AT90USBKey

This small board, about half the size of a business card, is priced at slightly more than an AVR Butterfly. It includes an at90usb1287 with USB-OTG support, 16 MB of DataFlash, LEDs, a small joystick, and a temperature sensor. It's clocked at 8 MHz, and comes with software which lets it act as a USB Mass Storage device (its documentation is shipped on the DataFlash), a USB joystick, and more. To support the USB host capability, it must be operated from a battery; but when running as a USB peripheral, it only needs the power provided over USB.

Only the JTAG port uses conventional 2.54mm pinout. All the other AVR I/O ports require more compact 1.27mm headers, which are not widely supported.

Since it has 128 KB of flash memory, a JTAGICE mkII is the best debug solution; a Dragon can program it, but can't examine its status. You can also program it through USB from a Windows or Linux host, using the USB "Device Firmware Update" protocols.

[edit] Raven Wireless Kit

The RAVEN kit supports wireless development using Atmel's IEEE 802.15.4 chipsets, for ZigBee and other wireless stacks. It resembles a pair of wireless more-powerful Butterfly cards, plus a wireless USBKey; and costing about that much (under $US100). All these boards support JTAG based development.

The kit includes two AVR Raven boards, each with 2.4 GHz transceiver supporting IEEE 802.15.4 (and a freely licensed ZigBee stack). The radios are driven with ATmega1284p processors, which are supported by a custom segmented LCD display driven by an ATmega3290p processor. Raven peripherals resemble the Butterfly: piezo speaker, DataFlash (bigger), external EEPROM, sensors, 32K crystal for RTC, and so on. These are intended for use developing remote sensor nodes, to control relays, or whatever is needed.

The USB stick uses an AT90usb1287 for connections to a USB host and to the 2.4 GHz wireless links. These are intended to monitor and control the remote nodes, relying on host power rather than local batteries.

[edit] Third-Party Programmers

A wide variety of third-party programming and debugging tools are available for the AVR. These devices use various interfaces, including RS-232, PC parallel port, and USB. AVR Freaks has a comprehensive list.

[edit] Atmel AVR Usage

AVRs have been used in various automotive applications such as security, safety, powertrain and entertainment systems. Atmel has recently launched a new publication "Atmel Automotive Compilation" to help developers with automotive applications. Some current usages are in BMW, Daimler-Chrysler and TRW.

The Arduino physical computing platform is based on an ATMega168 (or ATmega8 in older versions) processor.

USB-based AVRs have been used in the Microsoft Xbox hand controllers. The link between the controllers and Xbox is USB.

Lego has recently released the firmware source code files for 8-bit AVRs to aid in the development of open-source alternatives to its popular robotics NXT "brick" operating system.

Several companies produce AVR-based microcontrollers intended for use by hobbyists, robot builders, experimenters and small system developers (many of which are pin compatible with the PIC-based Basic Stamp) including Cubloc, BasicX, Oak Micros, and ZX Microcontrollers.

System Semiconductor,Inc recently released the "System on a Chip", which is a Motor and Motion Control Chip, the M3000 with an Atmel AVR Core married to an Advanced Motion Controller for use in a variety of motion applications.

[edit] The New 32-Bit AVRs

Main article: AVR32

In 2006 Atmel released microcontrollers based on the new, 32-bit, AVR32 architecture. They include SIMD and DSP instructions, along with other audio and video processing features. This 32-bit family of devices is intended to compete with the ARM based processors. The instruction set is similar to other RISC cores, but is not compatible with the original AVR or any of the various ARM cores.

[edit] Footnotes

1. ^ Since 1996, NTH has become part of the Norwegian University of Science and Technology (NTNU)
2. ^ AVR Television » Blog Archive » Special: The Story of AVR
3. ^ www.atmel.com/atmel/acrobat/1065s.pdf

[edit] External links

• Atmel AVR Homepage
• AVR Freaks community
• Atmel AVR at the Open Directory Project

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