65 nanometer

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CMOS manufacturing
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The 65 nanometer (65 nm) process is an advanced lithographic node used in volume CMOS semiconductor fabrication. Printed linewidths (i.e., transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process. See Table 40a in the 2006 industry roadmap [1]. For reference, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. The pitch between two lines drawn at 65 nm may be greater than 130 nm, though. Intel, AMD, IBM, UMC, Chartered and TSMC are currently producing 65 nm chips. Companies planning 65 nm production include Texas Instruments, Cypress Semiconductor and Motorola.

While feature sizes may be drawn as 65 nm or less, the wavelengths of light used for lithography are 193 nm and 248 nm. Fabrication of sub-wavelength features requires special imaging technologies, such as optical proximity correction and phase-shifting masks. Many of these techniques incur marginal costs in addition to those associated with upgrading equipment such as steppers and supplies such as photoresist. Furthermore, these costs are multiplied by an increasing number of mask layers that must be printed at the minimum pitch, and the reduction in yield from printing so many layers at the cutting edge of the technology. For new integrated circuit designs, this factors into the costs of prototyping and production. Upgraded 90-nanometer processes now compete with the 65 nm node from the same vendor, blurring the line between old and new technology.

Gate thickness, another important dimension, is reduced to as little as 1.2 nm (Intel). Only a few atoms insulate the "switch" part of the transistor, causing charge to flow through it. This undesired effect, leakage, is caused by quantum tunneling. The new chemistry of high-k gate dielectrics must be combined with existing techniques including substrate bias and multiple threshold voltages to prevent leakage from prohibitively consuming power.

IEDM papers from Intel in 2002, 2004 and 2005 indicate that the minimum feature pitch did not change much (220 nm to 210 nm) going from 90 nm to 65 nm node, even for the low power process. This suggests that scaling down the distance between microprocessor transistors is slowing down dramatically, but chip size can be made smaller by crowding a larger fraction of transistors at the minimum distance.