45 nanometer

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CMOS manufacturing processes

10 µm 3 µm 1.5 µm 1 µm 800 nm (0.80 µm) 600 nm (0.60 µm) 350 nm (0.35 µm) 250 nm (0.25 µm) 180 nm (0.18 µm) 130 nm (0.13 µm) 90 nm 65 nm 45 nm 32 nm (Double Patterning) 22 nm (End of Planar Bulk CMOS) 16 nm (Transition to Nanoelectronics) 11 nm (Nanoelectronics)

Per the International Technology Roadmap for Semiconductors, the 45 nm technology node should refer to the average half-pitch of a memory cell manufactured at around the 2007-2008 time frame.

Matsushita and Intel started mass producing 45 nm chips in 2007, and AMD is targeting 45 nm production in 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. By the end of 2008, SMIC will be the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM.

Many critical feature sizes are smaller than the wavelength of light used for lithography, i.e., 193 nm and/or 248 nm. A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lithography is used. It is expected that more layers will be patterned with 193 nm wavelength at the 45 nm node. Moving previously loose layers (such as Metal 4 and Metal 5) from 248 nm to 193 nm wavelength is expected to continue, which will likely further drive costs upward, due to difficulties with 193 nm photoresists.

Contents 1 High-k Dielectrics 2 Technology demos 3 Commercial introduction 4 Intel's 45 nm Process 5 References 6 External links

[edit] High-k Dielectrics

Chipmakers have initially voiced concerns about introducing new high-k materials into the gate stack, for the purpose of reducing leakage current density. As of 2007, however, both IBM and Intel have announced that they have high-k dielectric and metal gate solutions, which Intel considers to be a fundamental change in transistor design.^[1] NEC has also put high-k materials into production.

[edit] Technology demos

• In 2004, TSMC demonstrated a 0.296 square micrometer 45 nm SRAM cell. In 2008, TSMC moved on to a "40 nm" process.
• In January 2006, Intel demonstrated a 0.346 square micrometers 45 nm node SRAM cell.
• In April 2006, AMD demonstrated a 0.370 square micrometer 45 nm SRAM cell.
• In June 2006, Texas Instruments debuted a 0.24 square micrometer 45 nm SRAM cell, with the help of immersion lithography.
• In November 2006, UMC announced that it had developed a 45 nm SRAM chip with a cell size of less than 0.25 square micrometer using immersion lithography and low-k dielectrics.
• In June 2007 Matsushita Electric Industrial Co. started mass production of System-on-a-chip (SoC) for use in digital consumer equipment based on the 45-nm process technology.

The successors to 45 nm technology will be 32 nm, 22 nm, and then 16 nm technology per ITRS.

[edit] Commercial introduction

Matsushita Electric Industrial Co. has already started mass production of System-on-a-chip (SoC) for use in digital consumer equipment based on the 45-nm process technology.

Intel has shipped its first 45 nanometer based processor on the 5400-series Xeon(R) platform in November 2007.

Many details about Penryn appeared at the April 2007 Intel Developer Forum. Its successor is expected to be Nehalem. Important advances^[2] include the addition of new instructions (including SSE4, also known as Penryn New Instructions) and new fabrication materials (most significantly a hafnium-based dielectric).

AMD has targeted its commercial production for 2008. [1]

[edit] Intel's 45 nm Process

At IEDM 2007, more technical details of Intel's 45 nm process were revealed.

Since immersion lithography is not used here, the lithographic patterning is more difficult. Hence many lines have been lengthened rather than shortened. Double patterning is used explicitly for this 45 nm process, resulting in potentially higher risk of product delays than before. Also, the use of high-k dielectrics is introduced for the first time, to address gate leakage issues. For the 32 nm node, immersion lithography will begin to be used by Intel.

• 160 nm gate pitch (73% of 65 nm generation)
• 35 nm gate length (same as 65 nm generation)
• 1 nm equivalent oxide thickness, with 7 Å transition layer
• gate-last process using dummy polysilicon
• 9 layers of carbon-doped oxide and Cu interconnect, the last being a thick "redistribution" layer
• contacts shaped more like rectangles than circles for local interconnection
• lead-free packaging
• 1.36 mA/um nFET drive current
• 1.07 mA/um pFET drive current, 51% faster than 65 nm generation, with higher hole mobility due to increase from 23% to 30% Ge in embedded SiGe stressors

In a recent Chipworks reverse-engineering analysis, it was disclosed that the trench contacts were formed as a "Metal-0" layer in tungsten serving as a local interconnect. Most trench contacts were short lines oriented parallel to the gates covering diffusion, while gate contacts where even shorter lines oriented perpendicular to the gates.

[edit] References

1. ^ IEEE Spectrum: The High-k Solution
2. ^ Report on Penryn Series Improvements.. Intel (October 2006).

[edit] External links

• Panasonic Begins Mass Production of 45-nm Generation SoC
• Intel 45 nm process is good to go
• Intel moving to 45nm sooner than expected?
• Chipmakers gear up for manufacturing hurdles
• Intel 45 nm node SRAM cell
• An AMD Update
• Slashdot discussion of n nm process naming
• 45 nm Technology from Intel
• Intel 45 nm process at IEDM

Preceded by 65 nm

CMOS manufacturing processes

Succeeded by 32 nm