31-bit
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In computer architecture, 31-bit integers, memory addresses, or other data units are those that are at most 31 bits (32 bits minus 1 unused/reserved bit) wide. Also, 31-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size.
Perhaps the only computing architecture based on 31-bit addressing is one of computing's most famous and most profitable. In 1983, IBM introduced 31-bit addressing in the System/370-XA mainframe architecture as an upgrade to the 24-bit addressing of earlier models. This enhancement allowed address spaces to be 128 times larger, permitting programs to address memory above 16 MiB (referred to as "above the line").
In the System/360 and early System/370 architectures, addresses were always stored in 32-bit words, but the machines ignored the top 8 bits of the address resulting in 24-bit addressing. With the XA extension, no bits in the word were ignored.
The transition was tricky: assembly language programmers had been using the spare byte at the top of addresses for flags for almost twenty years. IBM chose to support two forms of addressing to minimize the pain: if the most significant bit (bit 0) of a 32-bit address was on, the next 31 bits were interpreted as the virtual address. If the most significant bit was off, then only the lower 24 bits were treated as the address (just as with pre-XA systems). Thus programs could continue using the seven low-order bits of the top byte for other purposes as long as they left the top bit off. The only programs requiring modification were those that set the top (leftmost) bit of a word containing an address. This also affected address comparisons: The leftmost bit of a word is also interpreted as a sign-bit, indicating a negative number if bit 0 is on. Programs that use signed arithmetic comparison instructions could get reversed results. Two equivalent addresses could be compared as non-equal if one of them had the sign bit turned on even if the remaining bits were identical. Fortunately, most of this was invisible to programmers using high-level languages like COBOL or FORTRAN, and IBM aided the transition with dual mode hardware for a period of time.
Certain machine instructions in this 31-bit architecture alter the addressing mode bit as a possibly intentional side effect. For example, the original subroutine call instruction BAL stores certain status information in the top byte of the return address. A BAS instruction was added to support 31-bit return addresses.
In the 1990s IBM introduced 370/ESA architecture (later named 390/ESA and finally ESA/390 or System/390, in short S/390), completing the evolution to full 31-bit virtual addressing and keeping this addressing mode flag. These later architectures support more than 2 GiB of physical memory and support multiple concurrent address spaces up to 2 GiB each in size. As of mid-2006 there still are not too many programs unduly constrained by this multiple 31-bit architecture.
Nonetheless, IBM broke the 2 GiB linear addressing barrier ("the bar") in 2000 with the introduction of the first 64-bit z/Architecture system, the IBM zSeries Model 900. Unlike the XA transition, z/Architecture does not reserve a top bit to identify earlier code. Yet z/Architecture does maintain compatibility with 24-bit and 31-bit code, even older code running concurrently with newer 64-bit code.
Since Linux/390 was first released for the existing 32-bit data/31-bit addressing hardware in 1999, initial mainframe Linux applications compiled in pre-z/Architecture mode are also limited to 31-bit addressing. This limitation disappeared with 64-bit hardware, 64-bit Linux on zSeries, and 64-bit Linux applications. The 64-bit Linux distributions still support 31-bit programs.
IBM's 31-bit architecture supports expanded storage, allowing 31-bit code to make use of additional memory. However, at any one instant, a maximum of 2 GiB is in each working address space. For 31-bit Linux it is possible to assign memory above the 2 GiB bar as a RAM disk.
