26-bit

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In ARM processor architecture, 26-bit refers to the design used in the original ARM processors, where the Program Counter(PC) and Processor Status Register(PSR) were combined into one 32-bit register (R15), the Status flags filling the high 6 bits and the Program Counter taking up the lower "26" bits. (The Program Counter is always word-aligned, so the lowest two bits are always zero. The designers took advantage of this and used these two bits of the PC to hold the processor's mode bits.)

This design enabled more efficient program execution, as the Program Counter and Status flags could be saved and restored with a single operation. This resulted in faster subroutine calls and interrupt response than traditional designs, which would have to do two register load/saves when calling or returning from a subroutine.

[edit] History

Despite being 32-bit internally, processors prior to the ARM6 had only a 26-bit PC and address bus, and were consequently limited to 64MB of addressable memory. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.

The ARM6 introduced a 32-bit PC and separate PSR, as well as a 32-bit address bus, allowing 4GB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility mode which used the old PC/PSR combination. The processor could still address 4GB in this mode, but could not execute anything above address 3FFFFFC (64MB). This mode was used by RISC OS running on the Acorn Risc PC to utilise the new processors while retaining compatibility with existing software.

More recent ARM architectures such as Intel's XScale have dropped the 26-bit mode altogether.

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