22 nanometer

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CMOS manufacturing
processes

10 µm
3 µm
1.5 µm
1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm (Double Patterning)
22 nm (End of Planar Bulk CMOS)
16 nm (Transition to Nanoelectronics)
11 nm (Nanoelectronics)

The 22 nanometer (22 nm) node is the CMOS process step following 32 nm. It is expected to be reached by semiconductor companies in the 2011-2012 timeframe. At that time, the typical half-pitch for a memory cell would be around 22 nm. The exact naming of this technology node comes from the International Technology Roadmap for Semiconductors (ITRS).

The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point.

It should be noted that even for electron beam lithography or extreme ultraviolet lithography, a 22 nm line/space pattern of good quality (e.g., low edge roughness) is hard to produce in resist. Since photolithography requires using double patterning at the 32 nm node, it is likely that this approach will continue to be used at the 22 nm node, in conjunction with hyper-NA (numerical aperture) immersion lithography tools.

Some predictions for the 22 nm node come from the ITRS. For example, it is predicted that silicon devices will no longer be planar, but will require ultrathin sections mostly surrounded on the sides by gates. The silicon body in each section is fully depleted, i.e., the free charge carrier concentration is deliberately suppressed. The sections basically protrude as fins from the surface (sometimes these are known as FinFETs). The creation of fins is a new challenge for the semiconductor industry, which has become accustomed to building transistors on a flat silicon surface.

According to the ITRS, the 22 nm node also marks the first time where the pre-metal dielectric, separating the transistor from the first metal layer, is a porous low-k material, replacing traditional, denser CVD silicon dioxide. The introduction of a porous material closer to the front end presents numerous integration challenges. In particular, the extent of plasma damage to low-k materials damage is typically 20 nm thick,^[1] but can also go up to approximately 100 nm.^[2]

The successor to 22 nm technology will be 16 nm technology per ITRS.