X86 instruction listings
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- The correct title of this article is x86 instruction listings. The initial letter is shown capitalized due to technical restrictions.
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[edit] Introduction
The x86 instruction set has undergone numerous changes over time. Most of them were to add new functionality to the instruction set.
[edit] x86 Integer Instructions
This is the full 8086-8088 instruction set, but most, if not all of these instructions are available in 32-bit mode, they just operate on 32 bit registers (eax, ebx, etc) and values instead of their 16-bit (ax, bx, etc) counterparts. See also x86 assembly language for a quick tutorial for this chip.
[edit] Original 8086/8088 instructions
| Instruction | Meaning | Notes |
|---|---|---|
| AAA | ASCII adjust AL after addition | used with unpacked binary coded decimal |
| AAD | ASCII adjust AX before division | buggy in the original instruction set, but "fixed" in the NEC V20, causing a number of incompatibilites |
| AAM | ASCII adjust AX after multiplication | |
| AAS | ASCII adjust AL after subtraction | |
| ADC | Add with carry | |
| ADD | Add | |
| AND | Logical AND | |
| CALL | Call procedure | |
| CBW | Convert byte to word | |
| CLC | Clear carry flag | |
| CLD | Clear direction flag | |
| CLI | Clear interrupt flag | |
| CMC | Complement carry flag | |
| CMP | Compare operands | |
| CMPSB | Compare bytes in memory | |
| CMPSW | Compare words | |
| CWD | Convert word to doubleword | |
| DAA | Decimal adjust AL after addition | (used with packed binary coded decimal) |
| DAS | Decimal adjust AL after subtraction | |
| DEC | Decrement by 1 | |
| DIV | Unsigned divide | |
| ESC | Used with floating-point unit | |
| HLT | Enter halt state | |
| IDIV | Signed divide | |
| IMUL | Signed multiply | |
| IN | Input from port | |
| INC | Increment by 1 | |
| INT | Call to interrupt | |
| INTO | Call to interrupt if overflow | |
| IRET | Return from interrupt | |
| Jxx | Jump if condition | (JA, JAE, JB, JBE, JC, JCXZ, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ) |
| JMP | Jump | |
| LAHF | Load flags into AH register | |
| LDS | Load pointer using DS | |
| LEA | Load Effective Address | |
| LES | Load ES with pointer | |
| LOCK | Assert BUS LOCK# signal | (for multiprocessing) |
| LODSB | Load byte | |
| LODSW | Load word | |
| LOOP/LOOPx | Loop control | (LOOPE, LOOPNE, LOOPNZ, LOOPZ) |
| MOV | Move | |
| MOVSB | Move byte from string to string | |
| MOVSW | Move word from string to string | |
| MUL | Unsigned multiply | |
| NEG | Two's complement negation | |
| NOP | No operation | |
| NOT | Negate the operand, logical NOT | |
| OR | Logical OR | |
| OUT | Output to port | |
| POP | Pop data from stack | |
| POPF | Pop data into flags register | |
| PUSH | Push data onto stack | |
| PUSHF | Push flags onto stack | |
| RCL | Rotate left (with carry) | |
| RCR | Rotate right (with carry) | |
| REPxx | Repeat CMPS/MOVS/SCAS/STOS | (REP, REPE, REPNE, REPNZ, REPZ) |
| RET | Return from procedure | |
| RETN | Return from near procedure | |
| RETF | Return from far procedure | |
| ROL | Rotate left | |
| ROR | Rotate right | |
| SAHF | Store AH into flags | |
| SAL | Shift Arithmetically left (multiply) | |
| SAR | Shift Arithmetically right (signed divide) | |
| SBB | Subtraction with borrow | |
| SCASB | Compare byte string | |
| SCASW | Compare word string | |
| SHL | Shift left (multiply) | |
| SHR | Shift right (unsigned divide) | |
| STC | Set carry flag | |
| STD | Set direction flag | |
| STI | Set interrupt flag | |
| STOSB | Store byte in string | |
| STOSW | Store word in string | |
| SUB | Subtraction | |
| TEST | Logical compare (AND) | |
| WAIT | Wait until not busy | Waits until BUSY# pin is inactive (used with floating-point unit) |
| XCHG | Exchange data | |
| XLAT | Table look-up translation | |
| XOR | Exclusive OR |
[edit] Added in specific processors
BOUND, ENTER, INSB, INSW, LEAVE, OUTSB, OUTSW, POPA, PUSHA, PUSHW
Added with 80286
ARPL, CLTS, LAR, LGDT, LIDT, LLDT, LMSW, LOADALL, LSL, LTR, SGDT, SIDT, SLDT, SMSW, STR, VERR, VERW
Added with 80386
BSF, BSR, BT, BTC, BTR, BTS, CDQ, CMPSD, CWDE, INSD, IRETD, IRETDF, IRETF, JECXZ, LFS, LGS, LSS, LODSD, LOOPD, LOOPED, LOOPNED, LOOPNZD, LOOPZD, MOVSD, MOVSX, MOVZX, OUTSD, POPAD, POPFD, PUSHAD, PUSHD, PUSHFD, SCASD, SETA, SETAE, SETB, SETBE, SETC, SETE, SETG, SETGE, SETL, SETLE, SETNA, SETNAE, SETNB, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNL, SETNLE, SETNO, SETNP, SETNS, SETNZ, SETO, SETP, SETPE, SETPO, SETS, SETZ, SHLD, SHRD, STOSD
Added with 80486
BSWAP, CMPXCHG, CPUID, INVD, INVLPG, RSM, WBINVD, XADD
Added with Pentium
CMPXCHG8B, RDMSR, RDPMC*, RDTSC, WRMSR
- RDPMC was introduced in the Pentium Pro processor and the Pentium processor with MMX technology.
Added with Pentium Pro
CMOVA, CMOVAE, CMOVB, CMOVBE, CMOVC, CMOVE, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE, CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG, CMOVNGE, CMOVNL, CMOVNLE, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO, CMOVS, CMOVZ, SYSENTER, SYSEXIT
Added with AMD K6-2
SYSCALL, SYSRET (functionally equivalent to SYSENTER and SYSEXIT)
Added with Pentium III
as part of the SSE branding
MASKMOVQ, MOVNTPS, MOVNTQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE (for Cacheability and Memory Ordering)
Added with Pentium 4
as part of the SSE2 branding
CLFLUSH, LFENCE, MASKMOVDQU, MFENCE, MOVNTDQ, MOVNTI, MOVNTPD, PAUSE (for Cacheability)
Added with Pentium 4 supporting SSE3
only on processors supporting Hyper-threading
as part of the SSE3 branding
MONITOR, MWAIT (for thread synchronization)
Added with Pentium 4 6x2
VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, VMXON (VMX instructions of VT)
Added with K8 supporting AMD-V
CLGI, SKINIT, STGI, VMLOAD, VMMCALL, VMRUN, VMSAVE (SVM instructions of AMD-V)
Added with x86-64
CMPXCHG16B, SWAPGS, CQO, CDQE
[edit] x87 Floating Point Instructions
[edit] Original 8087 instructions
F2XM1, FABS, FADD, FADDP, FBLD, FBSTP, FCHS, FCLEX, FCOM, FCOMP, FCOMPP, FDECSTP, FDISI, FDIV, FDIVP, FDIVR, FDIVRP, FENI, FFREE, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FINCSTP, FINIT, FIST, FISTP, FISUB, FISUBR, FLD, FLD1, FLDCW, FLDENV, FLDENVW, FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI, FLDZ, FMUL, FMULP, FNCLEX, FNDISI, FNENI, FNINIT, FNOP, FNSAVE, FNSAVEW, FNSTCW, FNSTENV, FNSTENVW, FNSTSW, FPATAN, FPREM, FPTAN, FRNDINT, FRSTOR, FRSTORW, FSAVE, FSAVEW, FSCALE, FSQRT, FST, FSTCW, FSTENV, FSTENVW, FSTP, FSTSW, FSUB, FSUBP, FSUBR, FSUBRP, FTST, FWAIT, FXAM, FXCH, FXTRACT, FYL2X, FYL2XP1
[edit] Added in specific processors
Added with 80287
FSETPM
Added with 80387
FCOS, FLDENVD, FNSAVED, FNSTENVD, FPREM1, FRSTORD, FSAVED, FSIN, FSINCOS, FSTENVD, FUCOM, FUCOMP, FUCOMPP
Added with Pentium Pro
- FCMOV variants: FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU
- FCOMI variants: FCOMI, FCOMIP, FUCOMI, FUCOMIP
- FXRSTOR, FXSAVE
Added with Pentium 4 supporting SSE3
as part of the SSE3 branding
FISTTP (x87 to integer conversion)
[edit] Undocumented instruction
FFREEP
[edit] SIMD Instructions
[edit] MMX instructions
added with Pentium MMX
EMMS, MOVD, MOVQ, PACKSSDW, PACKSSWB, PACKUSWB, PADDB, PADDD, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW, PAND, PANDN, PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW, PMADDWD, PMULHW, PMULLW, POR, PSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLQ, PSRLW, PSUBB, PSUBD, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBW, PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, PXOR
[edit] MMX+ instructions
added with Athlon
Same as SSE SIMD Integer Instructions
[edit] EMMX instructions
added with 6x86MX from Cyrix, deprecated now
PAVEB, PADDSIW, PMAGW, PDISTIB, PSUBSIW, PMVZB, PMULHRW, PMVNZB, PMVLZB, PMVGEZB, PMULHRIW, PMACHRIW
[edit] 3DNow! instructions
added with K6-2
FEMMS, PAVGUSB, PF2ID, PFACC, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQIT1, PFRSQRT, PFSUB, PFSUBR, PI2FD, PMULHRW, PREFETCH, PREFETCHW
[edit] 3DNow!+ instructions
added with K6-2+
PF2IW, PFNACC, PFPNACC, PI2FW, PSWAPD
[edit] SSE instructions
added with Pentium III
also see integer instruction added with Pentium III
[edit] SSE SIMD Floating-Point Instructions
ADDPS, ADDSS, ANDNPS, ANDPS, CMPPS, CMPSS, COMISS, CVTPI2PS, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, DIVPS, DIVSS, LDMXCSR, MAXPS, MAXSS, MINPS, MINSS, MOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVNTPS, MOVSS, MOVUPS, MULPS, MULSS, ORPS, RCPPS, RCPSS, RSQRTPS, RSQRTSS, SHUFPS, SQRTPS, SQRTSS, STMXCSR, SUBPS, SUBSS, UCOMISS, UNPCKHPS, UNPCKLPS, XORPS
[edit] SSE SIMD Integer Instructions
PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW
[edit] SSE2 instructions
added with Pentium 4
also see integer instructions added with Pentium 4
[edit] SSE2 SIMD Floating-Point Instructions
ADDPD, ADDSD, ANDNPD, ANDPD, CMPPD, CMPSD*, COMISD, CVTDQ2PD, CVTDQ2PS, CVTPD2DQ, CVTPD2PI, CVTPD2PS, CVTPI2PD, CVTPS2DQ, CVTPS2PD, CVTSD2SI, CVTSD2SS, CVTSI2SD, CVTSS2SD, CVTTPD2DQ, CVTTPD2PI, CVTPS2DQ, CVTTSD2SI, DIVPD, DIVSD, MAXPD, MAXSD, MINPD, MINSD, MOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVSD*, MOVUPD, MULPD, MULSD, ORPD, SHUFPD, SQRTPD, SQRTSD, SUBPD, SUBSD, UCOMISD, UNPCKHPD, UNPCKLPD, XORPD
- CMPSD and MOVSD have the same name as the string instruction mnemonics CMPSD (CMPS) and MOVSD (MOVS), however, the former refer to scalar double-precision floating-points whereas the latters refer to doubleword strings.
[edit] SSE2 SIMD Integer Instructions
MOVDQ2Q, MOVDQA, MOVDQU, MOVQ2DQ, PADDQ, PSUBQ, PMULUDQ, PSHUFHW, PSHUFLW, PSHUFD, PSLLDQ, PSRLDQ, PUNPCKHQDQ, PUNPCKLQDQ
[edit] SSE3 instructions
added with Pentium 4 supporting SSE3
also see integer and floating-point instructions added with Pentium 4 SSE3
[edit] SSE3 SIMD Floating-Point Instructions
- ADDSUBPD, ADDSUBPS (for Complex Arithmetic)
- HADDPD, HADDPS, HSUBPD, HSUBPS (for Graphics)
- MOVDDUP, MOVSHDUP, MOVSLDUP (for Complex Arithmetic)
[edit] SSE3 integer instructions
- LDDQU (for Video Encoding)
[edit] SSSE3 instructions
added with Xeon 5100 series and Core 2
- PSIGNW, PSIGND, PSIGNB
- PSHUFB
- PMULHRSW, PMADDUBSW
- PHSUBW, PHSUBSW, PHSUBD
- PHADDW, PHADDSW, PHADDD
- PALIGNR
- PABSW, PABSD, PABSB
[edit] External links
- Free IA-32 and x86-64 documentation, provided by Intel
- Netwide Assembler x86 Instruction Reference
