WinChip

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The WinChip C6 was designed and marketed by IDT as a low power x86 processor. The first design, launched in October 1997, ran 180-240 MHz. IDT launched WinChip 2 in 1998 with 3DNow! support at 200-240 MHz, and WinChip 2A (200-300 MHz) in early 1999.^[1]

The fundamental design of the WinChip was different from other processors of the time. Instead of a large gate count and die area, IDT, using experience from the RISC processor market, created a small and electrically efficient processor. In fact, Winchip had much in common with the 80486, because of its CISC/in-order design. This was dramatically different than its out-of-order x86 decoder-powered RISC peers, such as AMD K6 and Intel Pentium II.

Although the small die size and low power-usage made the processor extremely inexpensive to manufacture, it never gained much market share. The C6's performance was consistently below the equivalently-clocked Pentium or K6, especially in floating-point intensive tasks. Winchip 2's 3DNow! support improved this somewhat, but it was a subpar 3DNow! implementation that did not reach the K6-2's performance level.^[2] The industry's move away from Socket 7 and the release of the Intel Celeron processor signalled the end of the WinChip.

In 1999, the Centaur Technology division of IDT was sold to VIA. Although VIA initially branded processors as "Cyrix," the company used the WinChip technology in its Cyrix III line.

[edit] Core revisions under VIA

VIA Technologies launched the Cyrix III CPU in early 2000, and it was a bit of an oddity. VIA had fairly recently acquired both Cyrix and Centaur Technology. Pre-release Cyrix III CPUs were based upon a 22 million transistor Joshua core designed by Cyrix.^[3] When the chip reached reviewers, the CPU's performance was discovered to be abysmal compared to the competition. VIA then reimagined the Cyrix III with an 11 million transistor Centaur Technology-designed Samuel core.^[4] The Samuel core was an evolution of the Winchip design (the unreleased WinChip 4), designed for higher clock speeds, with more L1 cache (still no L2), and using newer, smaller manufacturing technology.^[5] While this Cyrix III's performance was still very sub-par, it was quite power efficient and consisted of only half the number of transistors of Cyrix's creation.^[5] The Samuel core did gain an on-die L2 cache after a revision, somewhat improving performance.^[6]

Cyrix III was later renamed C3, as it was not built upon Cyrix technology at all. Uniquely, the retail C3 CPU shipped inside a metal tin.^[7] The C3 processor continued an emphasis on minimizing power consumption, with VIA enjoying the lowest power usage in the x86 CPU market for several years. C3's performance, however, fell farther and farther behind due to the lack of improvements to the design, and Intel and AMD's continuing advancements.^[7] A half-speed FPU seriously crippled floating-point capabilities. C3 held a considerable power and cost advantage, however.

Processor	Speed (MHz)	FSB (MHz)	L1 cache (KiB)	L2 cache (KiB)	FPU Speed	Pipeline Stages	Max TDP (W)	Core (V)	Process (nm)
C3A (Samuel)	500-667	100/133	128	0	50%	12	8.5	1.9-2.0	180 Al
C3B (Samuel2)	700-800	100/133	128	64	50%	12	12	1.6-1.65	150 AL
C3C (Ezra-T)	800-950	100/133	128	64	50%	12	15	1.35	150/130 Al
C3M (Ezra-T)	800-950	100/133	128	64	50%	12	15	1.35	150/130 Cu
C3N (Ezra-T)	800-950	100/133	128	64	50%	12	15	1.35	130 Cu

[edit] References

^ Winchip experts: Help needed!, Google Groups, April, 1999.
^ IDT Winchip 2 266 Review, X-bit labs, April 18, 1999.
^ VIA Cyrix III, CPU Scorecard, October 8, 2005.
^ Witheiler, Matthew. [1] The New VIA Cyrix III: The Worlds First 0.15 Micron x86 CPU], Anandtech, January 5, 2001.
^ ^a ^b De Gelas, Johan. Cyrix III, An Alternative Approach, Ace's Hardware, August 6, 2000.
^ Poluvyalov, Alexander. VIA Cyrix III (Samuel 2) 600 and 667 MHz, Digit-Life, accessed January 15, 2007.
^ ^a ^b 800MHz Via C3 CPU, Dan's Data, September 29, 2001.