VIA C3

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The VIA C3 is an x86 central processing unit for personal computers produced by VIA Technologies. The C7 is one of several technical revisions VIA has undertaken to the original 16-stage pipeline core, adding new features.

Contents

[edit] Nehemiah core (C3, C3-M)

The C5X (Nehemiah) was a major core revision, technically different from the old WinChip (Centaur). At the time VIA's marketing efforts did not fully reflect the major changes that had taken place. The numerous design shortcomings of the Winchip core, including incomplete MMX compatibility and the half speed FPU, were addressed. The number of pipeline stages was also increased from 12 to 16, to allow increases in clock speed. However, it was still based upon the aging Socket 370, running at just 133 MHz.

VIA also appears to have realised in this period, that the small, cheap, low power characteristics of the chip, meant it was perfectly suited to high volume industrial orders in the embedded marketplace. With this in mind, in later revisions, VIA concentrated on adding features attractive to the embedded marketplace, for example in the C5XL Nehemiah VIA introduced the following:

  • Twin hardware random number generators. (These generators are erroneously called “quantum-based” in VIA's marketing literature. Detailed analysis of the generator makes clear that the source of randomness is thermal, not quantum.[1])

Extended in the C5P Nehemiah:

  • High performance AES encryption in hardware
  • A Ball grid array package the size of a 1 cent coin.

Antaur is a codename for mobile version of Nehemiah-based C3, also referred to as C3-M. It is clocked at 1000 MHz and has a TDP of 11 Watts.

[edit] Roadmap changes

According to VIA, the VIA C3 was to be superseded in 2003 by the VIA C4 - a clone of the Intel Pentium 4 processor. The VIA C4 naming was supposedly skipped because C4 is a high explosive (C3 is an explosive as well, but is lesser known than C4). In September 2004 VIA announced a change of naming policy, placing all their processors in the C3 or C7 category, with an M suffix for mobile devices. The C5P (Nehemiah) is now marketed as the C3 processor, most typically sold at 1.2 GHz. At one time the VIA roadmap predicted 3 GHz by Q4 2003 based upon the C4. The nanoBGA C3 package was discontinued, reportedly because at a mere 15mm by 15mm, it was so small manufacturers had problems designing motherboards to support it.

[edit] VIA C7 (Esther core)

VIA C7 Logo
VIA C7 Logo

The C7 delivers a number of improvements to the established C3 core, including a migration to a 90 nm silicon on insulator (SOI) manufacturing process developed by IBM Microelectronics (East Fishkill, New York). The chip was designed by the old Centaur team in Austin, Texas, by a permanent staff of a mere 85 engineers.

The C7 was officially launched in May 2005, although according to market reports, full volume production was not in place at that date. In May 2006 Intel's cross-licensing agreement with VIA expired and was not renewed, which was the reason for the forced termination of C3 shipments on March 31, 2006, as VIA lost rights to the 370 socket.

The C7 is sold in three main versions:

  • C7 for desktops / laptops (1.5-2.0 GHz) - FCPGA Pentium-M package, 400, 533, 800 MHz FSB
  • C7-M for mobiles / embedded (1.5-2.0 GHz) - NanoBGA2, 21mmx21mm, 400 MHz FSB
  • C7-M Ultra Low Voltage for mobiles / embedded (1.0-1.5 GHz) - NanoBGA2, 21mmx21mm, 400 MHz FSB

New Features for the C7 include:

  • Average power consumption of less than 1 watt
  • 2 GHz operation and a low TDP of 20 watts. For comparison, Dothan-core Pentium M processors need 21 (FSB 400) or 27 watts (FSB 533) to reach 2.0 GHz.
  • Level 2 cache increased from 64k to 128k, with associativity increased from 16-way set associative in C3 to 32-way set associative in C7.
  • VIA has stated the C7 bus is physically based upon the Pentium-M 479-pin packaging, but uses the proprietary VIA V4 bus for electrical signalling, instead of Intel’s AGTL+ Quad Pumped Bus, avoiding legal infringement. Reviewers have found it possible to insert both Pentium-M chips and C7s into the same motherboards, this is reportedly due to VIA's Flexi-Bus technology, which is claimed to auto-detect the CPU.
  • "Twin Turbo" technology, which consists of dual PLLs, one set at a high clock speed, and the other set at a lower speed. This allows the processor's clock frequency to be adjusted in a single processor cycle, much faster than the comparable Intel SpeedStep technology, providing enhanced power savings.
  • Support for SSE2 and SSE3 extended instructions.
  • NX flag to reduce buffer overflows and guard against viral attacks
  • Hardware support for SHA-1 and SHA-256 hashing.
  • Hardware based "Montgomery Multiplier" supporting key sizes up to 32K for public key cryptography

[edit] Core revisions

It has been suggested that this section be split into a new article entitled List of VIA microprocessors. (Discuss)

Somewhat confusingly, the term C3 was first used by VIA to describe the 130 nm process shrink of the old WinChip core. However, the term C3 has become commonly associated with the 16-pipeline stage, full speed FPU core C5X, which according the roadmap codenames, appears to have been planned to be called the C4 (abandoned as C4 is the name of an explosive), and later as the C5 (also abandoned).

Processor Speed
(MHz)		 FSB
(MHz)		 L1
cache
(KiB)		 L2
cache
(KiB)		 FPU
Speed		 Pipeline
Stages		 Max TDP
(W)		 Core
(V)		 Process
(nm)
C3C (Ezra-T) 800-950 100/133 128 64 50% 12 15 1.35 150/130 Al
C3M (Ezra-T) 800-950 100/133 128 64 50% 12 15 1.35 150/130 Cu
C3N (Ezra-T) 800-950 100/133 128 64 50% 12 15 1.35 130 Cu
C5X (Nehemiah) 1-1.4 GHz 133 128 64 100% 16 20 1.4-1.45 130 Cu
C5XL (Nehemiah) 1-1.4 GHz 133 128 64 100% 16 20 1.4-1.45 130 Cu
C5P (Nehemiah) 1-1.4 GHz 133 128 64 100% 16 20 1.4-1.45 130 Cu
C7-M (Esther C5-J) 1.5-2.0 GHz 400 128 128 100% 16 20 0.9-1.1 90 SOI
C7 (Esther C5-J) 1.5 / 1.7 / 2.0 GHz 400-800[citation needed] 128 128 100% 16 20 0.9-1.1 90 SOI

[edit] Comparative die size

Processor Secondary
Cache (k)		 Die size
130 nm (mm²)		 Die size
90 nm (mm²)
C3 / C7 64/128 52 30
Athlon XP 256 84 N/A
Athlon 64 512 144 84
Pentium M 2048 N/A 84
P4 Northwood 512 146 N/A
P4 Prescott 1024 N/A 110

NOTE: Even the 180 nm Duron Morgan core (106 mm²) with a mere 64 K secondary cache, when shrunk down to a 130 nm process, would have still had a die size of 76 mm². The VIA x86 core is clearly the smallest and cheapest to produce. As can be seen in this table, four C7 cores could be manufactured for the same cost as a single core P4 on 90 nm process.

[edit] Design methodology

A sub-notebook utilising a VIA Nehemiah C3 processor
A sub-notebook utilising a VIA Nehemiah C3 processor

While slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock for clock basis, VIA's chips are much smaller, cheaper to manufacture, and lower power. This makes them highly attractive in the embedded marketplace, and increasingly in the mobile sector as well.

This has also enabled VIA to continue to scale the frequencies of their chips, with each manufacturing process die shrink, while competitive products from Intel (such as the P4 Prescott) have encountered severe thermal management issues, although the new Intel Core generation of chips are substantially cooler.

To this extent, the performance gap that used to exist between VIA and competing x86 chips is still wide, but starting to narrow. Some of the design trade offs made by the VIA design team are worthy of study, as they run contrary to accepted wisdom.

[edit] C3

  • Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where they have not dropped features to save die space. In fact generous primary caches (128K) have always been a distinctive hallmark of Centaur / VIA designs.
  • Clock frequency is in general terms favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios. Internally, the C7 has 16 pipeline stages.
  • The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer pipeline clocks than on other x86 processors.
  • Infrequently used x86 instructions are implemented in microcode and emulated. This saves die space and reduces power consumption. The impact upon the majority of real world application scenarios is minimized.
  • These design guidelines are derivative from the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance. As it makes heavy use of memory operands, both as source and destination, the C3 design itself cannot qualify as RISC however.

[edit] C7

  • C7 Esther as an evolutionary step after C3 Nehemiah, in which VIA / Centaur followed their traditional approach of balancing performance against a constrained transistor / power budget.
  • The cornerstone of the C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache and branch prediction mechanisms.
  • In the case of C7, the design team have focused on further streamlining the "front-end" of the chip, i.e. cache size, associativity and throughput as well as the prefetch system.[2] At the same time no significant changes to the execution core ("back-end") of the chip seem to have been made.
  • The C7 successfully further closes the gap in performance with AMD / Intel chips, since clock speed is not thermally constrained.

[edit] Contracts

VIA’s embedded platform products have reportedly (2005) been adopted in Nissan’s car series, the Lafesta, Murano, and Presage. These and other high volume industrial applications are starting to generate big profits for VIA as the small form factor and low power advantages close embedded deals.

[edit] Legal issues

On the basis of the IDT Centaur acquisition,[3] VIA appears to have come into possession of at least three patents, which cover key aspects of processor technology used by Intel. On the basis of the negotiating leverage these patents offered, in 2003 VIA arrived at an agreement with Intel that allowed for a ten year patent cross license, enabling VIA to continue to design and manufacture x86 compatible CPUs. VIA was also granted a three year period of grace in which it could continue to use Intel socket infrastructure.

[edit] References

  1. ^ Evaluation of VIA C3 Nehemiah Random Number Generator. Cryptography Research, Inc.. Retrieved on 2007-03-12.
  2. ^ Detailed Platform Analysis in RightMark Memory Analyzer. Part 12: VIA C7/C7-M Processors. Digit-Life.com. Retrieved on 2007-03-12.
  3. ^ VIA and Intel Settle Patent Infringement Cases. VIA Technologies, Inc. Retrieved on 2007-03-12.

[edit] External links

[edit] C7

[edit] C3

[edit] General

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